From ebaf809be0661817947991be4839a1d07d657687 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 29 Jun 2019 06:09:34 +0100 Subject: [PATCH] update to table format --- simple_v_extension/vblock_format_table.mdwn | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/simple_v_extension/vblock_format_table.mdwn b/simple_v_extension/vblock_format_table.mdwn index c038a9536..fa74d1057 100644 --- a/simple_v_extension/vblock_format_table.mdwn +++ b/simple_v_extension/vblock_format_table.mdwn @@ -13,12 +13,12 @@ of the RISC-V ISA, is as follows: The VL/MAXVL/SubVL Block format: -| 31-30 | 29:28 | 27:22 | 21:17 | 16 | comment | -| - | ----- | ------ | ------ | - | -| -| 0b00 | SubVL | VLdest | imm[4:0] | imm | VL, bits 16-21 | -| 0b01 | SubVL | MVLimm | VLreg | VLd | VLdest=t0,t1 | -| 0b10 | SubVL | VLdest | imm[4:0] | imm | VL & MVL, bits 16-21 | -| 0b11 | rsvd | rsvd | rsvd | rsv | reserved, all 0s | - - +[[!table data=""" +31|30 | 29:28 | 27:22 | 21:17 | 16 | comment | +- | - | ----- | ------ | ------ | - | - | +0b00 || SubVL | VLdest | imm[4:0] | imm | VL, bits 16-21 | +0b01 || SubVL | MVLimm | VLreg | VLd | VLdest=t0,t1 | +0b10 || SubVL | VLdest | imm[4:0] | imm | VL & MVL, bits 16-21 | +0b11 || rsvd | rsvd | rsvd | rsv | reserved, all 0s | +"""]] -- 2.30.2