From ebb77b6f1ba475d193e97d0ed21c34c542388fa4 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Mon, 11 May 2020 10:04:07 -0400 Subject: [PATCH] Reorder the register reads so the field in read_reg2 is last --- src/soc/alu/test/test_pipe_caller.py | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py index 810d283c..5fe4cbc0 100644 --- a/src/soc/alu/test/test_pipe_caller.py +++ b/src/soc/alu/test/test_pipe_caller.py @@ -30,14 +30,14 @@ def set_alu_inputs(alu, dec2, sim): if reg1_ok: reg1_sel = yield dec2.e.read_reg1.data inputs.append(sim.gpr(reg1_sel).value) - reg2_ok = yield dec2.e.read_reg2.ok - if reg2_ok: - reg2_sel = yield dec2.e.read_reg2.data - inputs.append(sim.gpr(reg2_sel).value) reg3_ok = yield dec2.e.read_reg3.ok if reg3_ok: reg3_sel = yield dec2.e.read_reg3.data inputs.append(sim.gpr(reg3_sel).value) + reg2_ok = yield dec2.e.read_reg2.ok + if reg2_ok: + reg2_sel = yield dec2.e.read_reg2.data + inputs.append(sim.gpr(reg2_sel).value) print(inputs) @@ -152,7 +152,7 @@ class ALUTestCase(FHDLTestCase): with Program(lst) as program: sim = self.run_tst_program(program, initial_regs) - @unittest.skip("broken") + unittest.skip("broken") def test_shift(self): insns = ["slw", "sld", "srw", "srd", "sraw", "srad"] for i in range(20): @@ -165,6 +165,14 @@ class ALUTestCase(FHDLTestCase): with Program(lst) as program: sim = self.run_tst_program(program, initial_regs) + unittest.skip("broken") + def test_shift_imm(self): + lst = ["sradi 3, 1, 5"] + initial_regs = [0] * 32 + initial_regs[1] = random.randint(0, (1<<64)-1) + with Program(lst) as program: + sim = self.run_tst_program(program, initial_regs) + @unittest.skip("broken") def test_shift_arith(self): lst = ["sraw 3, 1, 2"] -- 2.30.2