From ec2cdd8d2bb373edb7e5db4b41338c801ed56d3a Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Fri, 2 Jun 2023 19:23:02 +0300 Subject: [PATCH] pysvp64asm: integrate into insndb --- setup.py | 2 +- src/openpower/decoder/isa/test_caller_setvl.py | 2 +- src/openpower/decoder/isa/test_caller_svindex.py | 2 +- src/openpower/decoder/isa/test_caller_svp64.py | 2 +- src/openpower/decoder/isa/test_caller_svp64_bc.py | 2 +- src/openpower/decoder/isa/test_caller_svp64_chacha20.py | 2 +- src/openpower/decoder/isa/test_caller_svp64_dct.py | 2 +- src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py | 2 +- src/openpower/decoder/isa/test_caller_svp64_fft.py | 2 +- src/openpower/decoder/isa/test_caller_svp64_fp.py | 2 +- src/openpower/decoder/isa/test_caller_svp64_inssort.py | 2 +- src/openpower/decoder/isa/test_caller_svp64_ldst.py | 2 +- src/openpower/decoder/isa/test_caller_svp64_mapreduce.py | 2 +- src/openpower/decoder/isa/test_caller_svp64_matrix.py | 2 +- src/openpower/decoder/isa/test_caller_svp64_pack.py | 2 +- src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py | 2 +- src/openpower/decoder/isa/test_caller_svp64_predication.py | 2 +- src/openpower/decoder/isa/test_caller_svp64_subvl.py | 2 +- src/openpower/decoder/isa/test_caller_svshape2.py | 2 +- src/openpower/decoder/isa/test_caller_svstate.py | 2 +- src/openpower/decoder/isa/test_caller_transcendentals.py | 2 +- src/openpower/{sv/trans/svp64.py => insndb/asm.py} | 2 +- src/openpower/sv/trans/test_pysvp64dis.py | 2 +- src/openpower/sv/trans/test_pysvp64dis_branch.py | 2 +- src/openpower/test/algorithms/svp64_utf_8_validation.py | 2 +- src/openpower/test/alu/fmvis_cases.py | 2 +- src/openpower/test/alu/maddsubrs_cases.py | 2 +- src/openpower/test/alu/svp64_cases.py | 2 +- src/openpower/test/bigint/bigint_cases.py | 2 +- src/openpower/test/bigint/shadd_cases.py | 2 +- src/openpower/test/bitmanip/av_cases.py | 2 +- src/openpower/test/bitmanip/bitmanip_cases.py | 2 +- src/openpower/test/fmv_fcvt/fmv_fcvt.py | 2 +- src/openpower/test/fptrans/fptrans_cases.py | 2 +- src/openpower/test/logical/svp64_cases.py | 2 +- src/openpower/test/mul/mul_cases.py | 2 +- src/openpower/test/prefix_codes/prefix_codes_cases.py | 2 +- src/openpower/test/svp64/parallel_prefix_sum.py | 2 +- 38 files changed, 38 insertions(+), 38 deletions(-) rename src/openpower/{sv/trans/svp64.py => insndb/asm.py} (99%) diff --git a/setup.py b/setup.py index 58a7ec32..304b2c95 100644 --- a/setup.py +++ b/setup.py @@ -82,7 +82,7 @@ setup( 'pyfnwriter=openpower.decoder.pseudo.pyfnwriter:pyfnwriter', 'sv_analysis=openpower.sv.sv_analysis:main', 'pypowersim=openpower.decoder.isa.pypowersim:run_simulation', - 'pysvp64asm=openpower.sv.trans.svp64:asm_process', + 'pysvp64asm=openpower.insndb.asm:main', 'pysvp64dis=openpower.sv.trans.pysvp64dis:main' ] } diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py index 163a5afe..a0661aa1 100644 --- a/src/openpower/decoder/isa/test_caller_setvl.py +++ b/src/openpower/decoder/isa/test_caller_setvl.py @@ -6,7 +6,7 @@ from openpower.decoder.isa.caller import CRFields, SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svindex.py b/src/openpower/decoder/isa/test_caller_svindex.py index e33ad652..2c479c2f 100644 --- a/src/openpower/decoder/isa/test_caller_svindex.py +++ b/src/openpower/decoder/isa/test_caller_svindex.py @@ -9,7 +9,7 @@ from openpower.decoder.isa.caller import SVP64State, set_masked_reg from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class SVSTATETestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64.py b/src/openpower/decoder/isa/test_caller_svp64.py index e5ef3f39..e38ba963 100644 --- a/src/openpower/decoder/isa/test_caller_svp64.py +++ b/src/openpower/decoder/isa/test_caller_svp64.py @@ -7,7 +7,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_bc.py b/src/openpower/decoder/isa/test_caller_svp64_bc.py index 159f08a2..23ba3b00 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_bc.py +++ b/src/openpower/decoder/isa/test_caller_svp64_bc.py @@ -7,7 +7,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_chacha20.py b/src/openpower/decoder/isa/test_caller_svp64_chacha20.py index 11ea2a08..0a0feac1 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_chacha20.py +++ b/src/openpower/decoder/isa/test_caller_svp64_chacha20.py @@ -9,7 +9,7 @@ from openpower.decoder.isa.caller import SVP64State, set_masked_reg from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm # originally from https://github.com/pts/chacha20 diff --git a/src/openpower/decoder/isa/test_caller_svp64_dct.py b/src/openpower/decoder/isa/test_caller_svp64_dct.py index 940724f9..581b3522 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_dct.py +++ b/src/openpower/decoder/isa/test_caller_svp64_dct.py @@ -12,7 +12,7 @@ from openpower.decoder.isafunctions.double2single import ( ISACallerFnHelper_double2single) from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm # really bad hack. need to access the DOUBLE2SINGLE function auto-generated # from pseudo-code. diff --git a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py index c9e98e48..666db4d2 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py +++ b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py @@ -6,7 +6,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py index fceb6b38..bc201c31 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_fft.py +++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py @@ -8,7 +8,7 @@ from openpower.decoder.isafunctions.double2single import ( ISACallerFnHelper_double2single) from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm # really bad hack. need to access the DOUBLE2SINGLE function auto-generated # from pseudo-code. diff --git a/src/openpower/decoder/isa/test_caller_svp64_fp.py b/src/openpower/decoder/isa/test_caller_svp64_fp.py index 703e95ab..920b21ad 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_fp.py +++ b/src/openpower/decoder/isa/test_caller_svp64_fp.py @@ -5,7 +5,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_inssort.py b/src/openpower/decoder/isa/test_caller_svp64_inssort.py index 86e706bb..816bb40b 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_inssort.py +++ b/src/openpower/decoder/isa/test_caller_svp64_inssort.py @@ -5,7 +5,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm def signcopy(x, y): diff --git a/src/openpower/decoder/isa/test_caller_svp64_ldst.py b/src/openpower/decoder/isa/test_caller_svp64_ldst.py index 8e37fce1..4ecf5347 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_ldst.py +++ b/src/openpower/decoder/isa/test_caller_svp64_ldst.py @@ -8,7 +8,7 @@ from openpower.decoder.isa.remap_dct_yield import halfrev2, reverse_bits from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm def write_byte(mem, addr, val): diff --git a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py index dbca7847..9d547ba9 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py +++ b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py @@ -6,7 +6,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py index 0796e7c9..65e0e341 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py +++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py @@ -7,7 +7,7 @@ from openpower.decoder.helpers import fp64toselectable from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_pack.py b/src/openpower/decoder/isa/test_caller_svp64_pack.py index e3edd216..0e83b9eb 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_pack.py +++ b/src/openpower/decoder/isa/test_caller_svp64_pack.py @@ -5,7 +5,7 @@ from openpower.decoder.isa.caller import CRFields, SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py b/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py index 88004682..c6ea8beb 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py +++ b/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py @@ -7,7 +7,7 @@ from openpower.decoder.isa.remap_preduce_yield import preduce_y from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm def signcopy(x, y): diff --git a/src/openpower/decoder/isa/test_caller_svp64_predication.py b/src/openpower/decoder/isa/test_caller_svp64_predication.py index a0552e75..0670abfb 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_predication.py +++ b/src/openpower/decoder/isa/test_caller_svp64_predication.py @@ -6,7 +6,7 @@ from openpower.decoder.isa.caller import CRFields, SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_subvl.py b/src/openpower/decoder/isa/test_caller_svp64_subvl.py index 01f1232e..cfd254d2 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_subvl.py +++ b/src/openpower/decoder/isa/test_caller_svp64_subvl.py @@ -6,7 +6,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svshape2.py b/src/openpower/decoder/isa/test_caller_svshape2.py index 53ae23c9..75aad211 100644 --- a/src/openpower/decoder/isa/test_caller_svshape2.py +++ b/src/openpower/decoder/isa/test_caller_svshape2.py @@ -9,7 +9,7 @@ from openpower.decoder.isa.caller import SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class SVSTATETestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svstate.py b/src/openpower/decoder/isa/test_caller_svstate.py index c8ef62c3..48c4b6f2 100644 --- a/src/openpower/decoder/isa/test_caller_svstate.py +++ b/src/openpower/decoder/isa/test_caller_svstate.py @@ -8,7 +8,7 @@ from openpower.decoder.isa.caller import CRFields, SVP64State from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class SVSTATETestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_transcendentals.py b/src/openpower/decoder/isa/test_caller_transcendentals.py index 6c6304f2..c61faa5d 100644 --- a/src/openpower/decoder/isa/test_caller_transcendentals.py +++ b/src/openpower/decoder/isa/test_caller_transcendentals.py @@ -8,7 +8,7 @@ from openpower.decoder.isafunctions.double2single import ( ISACallerFnHelper_double2single) from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm # really bad hack. need to access the DOUBLE2SINGLE function auto-generated # from pseudo-code. diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/insndb/asm.py similarity index 99% rename from src/openpower/sv/trans/svp64.py rename to src/openpower/insndb/asm.py index f05cefd1..8ed34b8d 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/insndb/asm.py @@ -169,7 +169,7 @@ def get_ws(line): return ws, line -def asm_process(): +def main(): # get an input file and an output file args = sys.argv[1:] if len(args) == 0: diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index 13c2152d..b8a8fe2b 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -1,6 +1,6 @@ from openpower.simulator.program import Program from openpower.sv.trans.pysvp64dis import load, dump -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm from openpower.insndb.types import Database, Style from openpower.decoder.power_enums import find_wiki_dir from openpower.sv import sv_binutils_fptrans diff --git a/src/openpower/sv/trans/test_pysvp64dis_branch.py b/src/openpower/sv/trans/test_pysvp64dis_branch.py index c809cba8..44a215fb 100644 --- a/src/openpower/sv/trans/test_pysvp64dis_branch.py +++ b/src/openpower/sv/trans/test_pysvp64dis_branch.py @@ -1,6 +1,6 @@ from openpower.simulator.program import Program from openpower.sv.trans.pysvp64dis import load, dump -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm from openpower.insndb.types import Database, Style from openpower.decoder.power_enums import find_wiki_dir from openpower.sv import sv_binutils_fptrans diff --git a/src/openpower/test/algorithms/svp64_utf_8_validation.py b/src/openpower/test/algorithms/svp64_utf_8_validation.py index 5174999c..054fd481 100644 --- a/src/openpower/test/algorithms/svp64_utf_8_validation.py +++ b/src/openpower/test/algorithms/svp64_utf_8_validation.py @@ -7,7 +7,7 @@ from openpower.decoder.selectable_int import SelectableInt from openpower.simulator.program import Program from openpower.test.common import TestAccumulatorBase, skip_case from openpower.test.state import ExpectedState -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm from cached_property import cached_property diff --git a/src/openpower/test/alu/fmvis_cases.py b/src/openpower/test/alu/fmvis_cases.py index 4689c26f..8caac0cf 100644 --- a/src/openpower/test/alu/fmvis_cases.py +++ b/src/openpower/test/alu/fmvis_cases.py @@ -1,4 +1,4 @@ -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm import random from openpower.test.common import TestAccumulatorBase from openpower.endian import bigendian diff --git a/src/openpower/test/alu/maddsubrs_cases.py b/src/openpower/test/alu/maddsubrs_cases.py index 7cb8f017..326060d4 100644 --- a/src/openpower/test/alu/maddsubrs_cases.py +++ b/src/openpower/test/alu/maddsubrs_cases.py @@ -1,4 +1,4 @@ -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm import random from openpower.test.common import TestAccumulatorBase, skip_case from openpower.endian import bigendian diff --git a/src/openpower/test/alu/svp64_cases.py b/src/openpower/test/alu/svp64_cases.py index 6c4b5289..b86a1d12 100644 --- a/src/openpower/test/alu/svp64_cases.py +++ b/src/openpower/test/alu/svp64_cases.py @@ -2,7 +2,7 @@ from openpower.test.common import (TestAccumulatorBase, skip_case) from openpower.endian import bigendian from openpower.simulator.program import Program from openpower.decoder.isa.caller import SVP64State, CRFields -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm from openpower.test.state import ExpectedState from copy import deepcopy diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py index 092c8468..38ad4e08 100644 --- a/src/openpower/test/bigint/bigint_cases.py +++ b/src/openpower/test/bigint/bigint_cases.py @@ -1,5 +1,5 @@ from openpower.test.common import TestAccumulatorBase, skip_case -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm from openpower.test.state import ExpectedState from openpower.simulator.program import Program from openpower.decoder.isa.caller import SVP64State diff --git a/src/openpower/test/bigint/shadd_cases.py b/src/openpower/test/bigint/shadd_cases.py index 1534a8ea..7e61e303 100644 --- a/src/openpower/test/bigint/shadd_cases.py +++ b/src/openpower/test/bigint/shadd_cases.py @@ -1,5 +1,5 @@ from openpower.test.common import TestAccumulatorBase, skip_case -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm from openpower.test.state import ExpectedState from openpower.simulator.program import Program from openpower.decoder.isa.caller import SVP64State diff --git a/src/openpower/test/bitmanip/av_cases.py b/src/openpower/test/bitmanip/av_cases.py index bfb4a350..d39e0441 100644 --- a/src/openpower/test/bitmanip/av_cases.py +++ b/src/openpower/test/bitmanip/av_cases.py @@ -1,4 +1,4 @@ -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm import random from openpower.test.common import TestAccumulatorBase from openpower.endian import bigendian diff --git a/src/openpower/test/bitmanip/bitmanip_cases.py b/src/openpower/test/bitmanip/bitmanip_cases.py index 8c344d5f..c89d3f81 100644 --- a/src/openpower/test/bitmanip/bitmanip_cases.py +++ b/src/openpower/test/bitmanip/bitmanip_cases.py @@ -1,4 +1,4 @@ -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm from openpower.test.common import TestAccumulatorBase, skip_case from openpower.endian import bigendian from openpower.simulator.program import Program diff --git a/src/openpower/test/fmv_fcvt/fmv_fcvt.py b/src/openpower/test/fmv_fcvt/fmv_fcvt.py index 613c0564..29c35146 100644 --- a/src/openpower/test/fmv_fcvt/fmv_fcvt.py +++ b/src/openpower/test/fmv_fcvt/fmv_fcvt.py @@ -1,5 +1,5 @@ from openpower.test.common import TestAccumulatorBase, skip_case -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm from openpower.test.state import ExpectedState from openpower.simulator.program import Program from openpower.decoder.isa.caller import SVP64State diff --git a/src/openpower/test/fptrans/fptrans_cases.py b/src/openpower/test/fptrans/fptrans_cases.py index bfa08165..92d84b5b 100644 --- a/src/openpower/test/fptrans/fptrans_cases.py +++ b/src/openpower/test/fptrans/fptrans_cases.py @@ -1,5 +1,5 @@ from openpower.test.common import TestAccumulatorBase, skip_case -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm from openpower.test.state import ExpectedState from openpower.simulator.program import Program from openpower.decoder.isa.caller import SVP64State diff --git a/src/openpower/test/logical/svp64_cases.py b/src/openpower/test/logical/svp64_cases.py index 000bc434..3cf2de13 100644 --- a/src/openpower/test/logical/svp64_cases.py +++ b/src/openpower/test/logical/svp64_cases.py @@ -2,7 +2,7 @@ from openpower.test.common import (TestAccumulatorBase, skip_case) from openpower.endian import bigendian from openpower.simulator.program import Program from openpower.decoder.isa.caller import SVP64State, CRFields -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm class SVP64LogicalTestCase(TestAccumulatorBase): diff --git a/src/openpower/test/mul/mul_cases.py b/src/openpower/test/mul/mul_cases.py index f1e7cc11..32ca0c30 100644 --- a/src/openpower/test/mul/mul_cases.py +++ b/src/openpower/test/mul/mul_cases.py @@ -2,7 +2,7 @@ from openpower.simulator.program import Program from openpower.endian import bigendian from openpower.test.common import TestAccumulatorBase, skip_case from openpower.test.state import ExpectedState -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm from openpower.decoder.isa.caller import SVP64State from copy import deepcopy import random diff --git a/src/openpower/test/prefix_codes/prefix_codes_cases.py b/src/openpower/test/prefix_codes/prefix_codes_cases.py index c19fa350..da2d85ef 100644 --- a/src/openpower/test/prefix_codes/prefix_codes_cases.py +++ b/src/openpower/test/prefix_codes/prefix_codes_cases.py @@ -1,7 +1,7 @@ import functools import itertools from openpower.test.common import TestAccumulatorBase, skip_case -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm from openpower.test.state import ExpectedState from openpower.simulator.program import Program from typing import Iterable diff --git a/src/openpower/test/svp64/parallel_prefix_sum.py b/src/openpower/test/svp64/parallel_prefix_sum.py index 74b408f4..36c08e1e 100644 --- a/src/openpower/test/svp64/parallel_prefix_sum.py +++ b/src/openpower/test/svp64/parallel_prefix_sum.py @@ -1,7 +1,7 @@ import itertools import operator from openpower.simulator.program import Program -from openpower.sv.trans.svp64 import SVP64Asm +from openpower.insndb.asm import SVP64Asm from openpower.test.state import ExpectedState from openpower.test.common import TestAccumulatorBase, skip_case from nmutil.prefix_sum import prefix_sum, prefix_sum_ops -- 2.30.2