From ec34632859f0420e0d1912357a96ec280ed87561 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 2 May 2017 15:32:32 +0200 Subject: [PATCH] radeonsi/gfx9: set VGT_REUSE_OFF = 0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit same as Vulkan Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_state.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 938e7fb06a9..e967b4b493c 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -717,9 +717,11 @@ static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom) ucp_mask | S_028810_CLIP_DISABLE(window_space)); - /* reuse needs to be set off if we write oViewport */ - radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF, - S_028AB4_REUSE_OFF(info->writes_viewport_index)); + if (sctx->b.chip_class <= VI) { + /* reuse needs to be set off if we write oViewport */ + radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF, + S_028AB4_REUSE_OFF(info->writes_viewport_index)); + } } /* @@ -4342,6 +4344,8 @@ static void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1); + if (sctx->b.chip_class >= GFX9) + si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0); si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); if (sctx->b.chip_class < CIK) si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | -- 2.30.2