From ec3fac0d6179bcfd9c8df9bb978e8b88ba416746 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 16 Mar 2020 10:34:05 +0000 Subject: [PATCH] Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility --- f4/6467307ccdc2edff1cec43d9f4d4c8b9b36368 | 78 +++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 f4/6467307ccdc2edff1cec43d9f4d4c8b9b36368 diff --git a/f4/6467307ccdc2edff1cec43d9f4d4c8b9b36368 b/f4/6467307ccdc2edff1cec43d9f4d4c8b9b36368 new file mode 100644 index 0000000..59a91eb --- /dev/null +++ b/f4/6467307ccdc2edff1cec43d9f4d4c8b9b36368 @@ -0,0 +1,78 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Mon, 16 Mar 2020 10:34:40 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jDn4x-00089V-TG; Mon, 16 Mar 2020 10:34:39 +0000 +Received: from lkcl.net ([217.147.94.29]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jDn4w-00089P-1F + for libre-riscv-dev@lists.libre-riscv.org; Mon, 16 Mar 2020 10:34:38 +0000 +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lkcl.net; + s=201607131; + h=Content-Type:To:Subject:Message-ID:Date:From:In-Reply-To:References:MIME-Version; + bh=RKknuCIbedaCKzeH14/Xhja7/pMriD30zuciDME7KGg=; + b=CDOQsiTMlSgpPm4IfC0GiBYPfcinvuUvKBYNG9thu6M5FyBgvP0gAdmir2mWlduFFzd+VV5SXKt3WozgwHxxW8hm9oDod2qCcYwdCUysKMbX343p0OP8u0vNsTLMHsTtupwO+c6RVsurSvqpaCK0oZy4XTq24PANsB0jU28R8Fc=; +Received: from mail-lf1-f54.google.com ([209.85.167.54]) + by lkcl.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.84_2) (envelope-from ) id 1jDn4v-0000DT-Mh + for libre-riscv-dev@lists.libre-riscv.org; Mon, 16 Mar 2020 10:34:37 +0000 +Received: by mail-lf1-f54.google.com with SMTP id 5so6439419lfr.2 + for ; + Mon, 16 Mar 2020 03:34:22 -0700 (PDT) +X-Gm-Message-State: ANhLgQ2dV5A69NNvzZ0DxMFsbuaAi0jhpTVAdDE81P3+dljfHnuC/XRo + bdzsD1Mb7ZzlTQGXnxdhYLxj7qo/TmIKK2+ClXs= +X-Google-Smtp-Source: ADFU+vv8O08j1Pqr19ofN5+5WwdOogxAoYB3nvBvDLQuyXjXCDvJIQ8cF698jGFzAIJ4162vP24jf0M8/NBmHgttFgM= +X-Received: by 2002:a19:4350:: with SMTP id m16mr8420309lfj.67.1584354856749; + Mon, 16 Mar 2020 03:34:16 -0700 (PDT) +MIME-Version: 1.0 +References: <6AC4EFD4-AA30-42C7-855A-CE68A62F107F@gatech.edu> + + <20200315051018.svaw4aor7ifwn725@topoi.pooq.com> + + + + <1BB9EA49-275B-4365-963E-9FC21D574BB7@gatech.edu> + <16F24775-E25B-4E31-A1D4-145EB65FB1D8@gatech.edu> + + <75CA4609-370F-455E-A88D-50E3766D45D7@gatech.edu> + + <884F8FEE-60FF-4580-A2E7-8AAA40A6DB6B@gatech.edu> + + <20200316091420.15087a26fab1be3d5fc23953@gmx.com> + + <20200316112700.bef98590e39c27ae3b1cb63d@gmx.com> +In-Reply-To: <20200316112700.bef98590e39c27ae3b1cb63d@gmx.com> +From: Luke Kenneth Casson Leighton +Date: Mon, 16 Mar 2020 10:34:05 +0000 +X-Gmail-Original-Message-ID: +Message-ID: +To: Libre-RISCV General Development +Subject: Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture + feasibility +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: text/plain; charset="utf-8" +Content-Transfer-Encoding: base64 +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + +aHR0cHM6Ly9naXRodWIuY29tL3Bvd2VyLWdlbTUKdGhpcyBib290cyBhIDY0LWJpdCBCRSBsaW51 +eCBrZXJuZWwsIHBsdXMgYSBiYXNpYyBpbml0cmFtZnMgYW5kIGhhcwp0ZWxuZXQgaW4gdG8gdGhl +IGNvbnNvbGUuCmwuCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f +X19fXwpsaWJyZS1yaXNjdi1kZXYgbWFpbGluZyBsaXN0CmxpYnJlLXJpc2N2LWRldkBsaXN0cy5s +aWJyZS1yaXNjdi5vcmcKaHR0cDovL2xpc3RzLmxpYnJlLXJpc2N2Lm9yZy9tYWlsbWFuL2xpc3Rp +bmZvL2xpYnJlLXJpc2N2LWRldgo= -- 2.30.2