From ec46904edfec162f32b8b411301374afc8f5fcb5 Mon Sep 17 00:00:00 2001
From: Joel Hutton <joel.hutton@arm.com>
Date: Thu, 19 Nov 2020 10:28:38 +0000
Subject: [PATCH] [1/3][aarch64] Add vec_widen patterns to aarch64

Add widening add and subtract patterns to the aarch64
backend. These allow taking vectors of N elements of size S
and performing and add/subtract on the high or low half
widening the resulting elements and storing N/2 elements of size 2*S.
These correspond to the addl,addl2,subl,subl2 instructions.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md: New patterns
	vec_widen_saddl_lo/hi_<mode>.
---
 gcc/config/aarch64/aarch64-simd.md | 47 ++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 2cf6fe9154a..e8c951fe55e 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3382,6 +3382,53 @@
   [(set_attr "type" "neon_<ADDSUB:optab>_long")]
 )
 
+(define_expand "vec_widen_<su>addl_lo_<mode>"
+  [(match_operand:<VWIDE> 0 "register_operand")
+   (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))
+   (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))]
+  "TARGET_SIMD"
+{
+  rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
+  emit_insn (gen_aarch64_<su>addl<mode>_lo_internal (operands[0], operands[1],
+						     operands[2], p));
+  DONE;
+})
+
+(define_expand "vec_widen_<su>addl_hi_<mode>"
+  [(match_operand:<VWIDE> 0 "register_operand")
+   (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))
+   (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))]
+  "TARGET_SIMD"
+{
+  rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
+  emit_insn (gen_aarch64_<su>addl<mode>_hi_internal (operands[0], operands[1],
+						     operands[2], p));
+  DONE;
+})
+
+(define_expand "vec_widen_<su>subl_lo_<mode>"
+  [(match_operand:<VWIDE> 0 "register_operand")
+   (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))
+   (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))]
+  "TARGET_SIMD"
+{
+  rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
+  emit_insn (gen_aarch64_<su>subl<mode>_lo_internal (operands[0], operands[1],
+						     operands[2], p));
+  DONE;
+})
+
+(define_expand "vec_widen_<su>subl_hi_<mode>"
+  [(match_operand:<VWIDE> 0 "register_operand")
+   (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))
+   (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))]
+  "TARGET_SIMD"
+{
+  rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
+  emit_insn (gen_aarch64_<su>subl<mode>_hi_internal (operands[0], operands[1],
+						     operands[2], p));
+  DONE;
+})
 
 (define_expand "aarch64_saddl2<mode>"
   [(match_operand:<VWIDE> 0 "register_operand")
-- 
2.30.2