From ec52e7d58f8062c91b7698ff9ce11bc5ddb8f3fc Mon Sep 17 00:00:00 2001 From: Andrew Pinski Date: Thu, 29 Apr 2004 20:23:36 +0000 Subject: [PATCH] rs6000-power2-1.c: Change the options to be more correct. 2004-04-29 Andrew Pinski * gcc.dg/rs6000-power2-1.c: Change the options to be more correct. * gcc.dg/rs6000-power2-2.c: Change the options to be more correct. Change the asm registers to be in form of frN instead of fN. From-SVN: r81303 --- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.dg/rs6000-power2-1.c | 2 +- gcc/testsuite/gcc.dg/rs6000-power2-2.c | 8 ++++---- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 718a92eb2dc..2214658bbbc 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2004-04-29 Andrew Pinski + + * gcc.dg/rs6000-power2-1.c: Change the options to be more correct. + * gcc.dg/rs6000-power2-2.c: Change the options to be more correct. + Change the asm registers to be in form of frN instead of fN. + 2004-04-28 Kaveh R. Ghazi * gcc.dg/torture/builtin-convert-2.c: New test. diff --git a/gcc/testsuite/gcc.dg/rs6000-power2-1.c b/gcc/testsuite/gcc.dg/rs6000-power2-1.c index 7f22b98c64e..0e9b5aa1d5d 100644 --- a/gcc/testsuite/gcc.dg/rs6000-power2-1.c +++ b/gcc/testsuite/gcc.dg/rs6000-power2-1.c @@ -1,5 +1,5 @@ /* { dg-do assemble { target powerpc-*-* rs6000-*-* } } */ -/* { dg-options "-O -mpower2 -fno-schedule-insns -w" } */ +/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */ /* This used to ICE as the peephole was not checking to see if the register is a floating point one (I think this cannot happen in real life except in this example). */ diff --git a/gcc/testsuite/gcc.dg/rs6000-power2-2.c b/gcc/testsuite/gcc.dg/rs6000-power2-2.c index dda48526c24..74cc0ec64e3 100644 --- a/gcc/testsuite/gcc.dg/rs6000-power2-2.c +++ b/gcc/testsuite/gcc.dg/rs6000-power2-2.c @@ -1,13 +1,13 @@ /* { dg-do assemble { target powerpc-*-* rs6000-*-* } } */ -/* { dg-options "-O -mpower2 -fno-schedule-insns" } */ +/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */ /* { dg-final { scan-assembler-not "lfd" } } */ /* { dg-final { scan-assembler-not "sfd" } } */ /* { dg-final { scan-assembler "lfq" } } */ /* { dg-final { scan-assembler "sfq" } } */ -register double t1 __asm__("f0"); -register double t2 __asm__("f1"); -register double t3 __asm__("f2"), t4 __asm__("f3"); +register double t1 __asm__("fr0"); +register double t2 __asm__("fr1"); +register double t3 __asm__("fr2"), t4 __asm__("fr3"); void t(double *a, double *b) { t1 = a[-1]; -- 2.30.2