From ec5a10380afde35e549d6cc78262d88bb1ac6479 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 7 May 2022 14:42:54 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index b9ee7598f..3ef9c84f7 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -568,7 +568,7 @@ came out with an astonishing 43% improvement in completion time. 43% less instructions executed is an almost unheard-of level of optimisation: most ISA designers are elated if they can achieve 5 to 10%. The reduction was so compelling that ST Microelectronics put it into commercial -production in one of their embedded CPUs. +production in one of their embedded CPUs, the ST120 DSP-MCU. The kicker: when implementing SVP64's Matrix REMAP Schedule, the VLSI design of its triple-nested for-loop system -- 2.30.2