From ec700197925daec5c3d81170c634a677a5cbbd1b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 19 Jul 2020 11:59:05 +0100 Subject: [PATCH] use iocontrol PrevControl / NextControl instead of dummy classes --- src/soc/experiment/alu_fsm.py | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py index 0ca1b118..001de5c2 100644 --- a/src/soc/experiment/alu_fsm.py +++ b/src/soc/experiment/alu_fsm.py @@ -21,6 +21,7 @@ from nmigen.back.pysim import Simulator from nmigen.cli import rtlil from soc.fu.cr.cr_input_record import CompCROpSubset from math import log2 +from nmutil.iocontrol import PrevControl, NextControl class Dummy: @@ -59,22 +60,12 @@ class Shifter(Elaboratable): def _get_data(self): return [self.data] - class PrevPort: - def __init__(self, width): - self.data_i = Shifter.PrevData(width) - self.valid_i = Signal(name="p_valid_i") - self.ready_o = Signal(name="p_ready_o") - - class NextPort: - def __init__(self, width): - self.data_o = Shifter.NextData(width) - self.valid_o = Signal(name="n_valid_o") - self.ready_i = Signal(name="n_ready_i") - def __init__(self, width): self.width = width - self.p = self.PrevPort(width) - self.n = self.NextPort(width) + self.p = PrevControl() + self.n = NextControl() + self.p.data_i = Shifter.PrevData(width) + self.n.data_o = Shifter.NextData(width) # more pieces to make this example class comply with the CompALU API self.op = CompCROpSubset() @@ -85,6 +76,9 @@ class Shifter(Elaboratable): def elaborate(self, platform): m = Module() + m.submodules.p = self.p + m.submodules.n = self.n + # Note: # It is good practice to design a sequential circuit as # a data path and a control path. -- 2.30.2