From ec7fd7807d5e1a06a8fe957d0e12df0753acb6c4 Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Tue, 4 Jun 2019 00:33:11 +0200 Subject: [PATCH] rs6000: Delete wg The "wg" constraint is used for the floating point side on mfpgpr instructions. Those instructions do not exist on any relevant hardware. This patch deletes the constraint and the insns using it. * config/rs6000/constraints.md (define_register_constraint "wg"): Delete. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete RS6000_CONSTRAINT_wg. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000.md (*mov_softfloat32, *movdi_internal64): Delete "wg" alternatives. * doc/md.texi (Machine Constraints): Adjust. From-SVN: r271888 --- gcc/ChangeLog | 12 ++++++++++++ gcc/config/rs6000/constraints.md | 3 --- gcc/config/rs6000/rs6000.c | 6 ------ gcc/config/rs6000/rs6000.h | 1 - gcc/config/rs6000/rs6000.md | 26 +++++++++++--------------- gcc/doc/md.texi | 5 +---- 6 files changed, 24 insertions(+), 29 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ae20f9579aa..80561d7fd6f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2019-06-03 Segher Boessenkool + + * config/rs6000/constraints.md (define_register_constraint "wg"): + Delete. + * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete + RS6000_CONSTRAINT_wg. + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. + (rs6000_init_hard_regno_mode_ok): Adjust. + * config/rs6000/rs6000.md (*mov_softfloat32, *movdi_internal64): + Delete "wg" alternatives. + * doc/md.texi (Machine Constraints): Adjust. + 2019-06-03 Alan Modra * bb-reorder.c (copy_bb_p): Don't overflow size calculation. diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 8004a92fd40..844e947ece6 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -68,9 +68,6 @@ (define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]" "VSX vector register to hold vector float data or NO_REGS.") -(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" - "If -mmfpgpr was used, a floating point register or NO_REGS.") - (define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 94795bec1d4..ba405365066 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2511,7 +2511,6 @@ rs6000_debug_reg_global (void) "wd reg_class = %s\n" "we reg_class = %s\n" "wf reg_class = %s\n" - "wg reg_class = %s\n" "wi reg_class = %s\n" "wp reg_class = %s\n" "wq reg_class = %s\n" @@ -2530,7 +2529,6 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]], @@ -3150,7 +3148,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) wc - Reserved to represent individual CR bits (used in LLVM). wd - Preferred register class for V2DFmode. wf - Preferred register class for V4SFmode. - wg - Float register for power6x move insns. wi - FP or VSX register to hold 64-bit integers for VSX insns. wn - always NO_REGS. wr - GPR if 64-bit mode is permitted. @@ -3182,9 +3179,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) if (TARGET_ALTIVEC) rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS; - if (TARGET_MFPGPR) /* DFmode */ - rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS; - if (TARGET_POWERPC64) { rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS; diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 34fa36b6ed9..8ec1f352751 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1260,7 +1260,6 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ - RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 47cbba89443..c8e43c5ced7 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7641,19 +7641,19 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSDX STXSDX XXLOR XXLXOR LI 0 ;; STD LD MR MT{CTR,LR} MF{CTR,LR} -;; NOP MFTGPR MFFGPR MFVSRD MTVSRD +;; NOP MFVSRD MTVSRD (define_insn "*mov_hardfloat64" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, , wY, , Z, , , !r, YZ, r, !r, *c*l, !r, - *h, r, wg, r, ") + *h, r, ") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , Z, , , , , r, YZ, r, r, *h, - 0, wg, r, , r"))] + 0, , r"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -7674,21 +7674,19 @@ mt%0 %1 mf%1 %0 nop - mftgpr %0,%1 - mffgpr %0,%1 mfvsrd %0,%x1 mtvsrd %x0,%1" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, integer, store, load, *, mtjmpr, mfjmpr, - *, mftgpr, mffgpr, mftgpr, mffgpr") + *, mftgpr, mffgpr") (set_attr "size" "64") (set_attr "isa" "*, *, *, p9v, p9v, *, *, *, *, *, *, *, *, *, *, - *, *, *, p8v, p8v")]) + *, p8v, p8v")]) ;; STD LD MR MT MF G-const ;; H-const F-const Special @@ -8825,20 +8823,20 @@ ;; FPR store FPR load FPR move AVX store AVX store AVX load ;; AVX load VSX move P9 0 P9 -1 AVX 0/-1 VSX 0 ;; VSX -1 P9 const AVX const From SPR To SPR SPR<->SPR -;; FPR->GPR GPR->FPR VSX->GPR GPR->VSX +;; VSX->GPR GPR->VSX (define_insn "*movdi_internal64" [(set (match_operand:DI 0 "nonimmediate_operand" "=YZ, r, r, r, r, r, m, ^d, ^d, wY, Z, $v, $wv, ^wi, wa, wa, wv, wi, wi, wv, wv, r, *h, *h, - ?r, ?wg, ?r, ?wi") + ?r, ?wi") (match_operand:DI 1 "input_operand" "r, YZ, r, I, L, nF, ^d, m, ^d, ^v, $wv, wY, Z, ^wi, Oj, wM, OjwM, Oj, wM, wS, wB, *h, r, 0, - wg, r, wi, r"))] + wi, r"))] "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) || gpc_reg_operand (operands[1], DImode))" @@ -8867,8 +8865,6 @@ mf%1 %0 mt%0 %1 nop - mftgpr %0,%1 - mffgpr %0,%1 mfvsrd %0,%x1 mtvsrd %x0,%1" [(set_attr "type" @@ -8876,20 +8872,20 @@ fpstore, fpload, fpsimple, fpstore, fpstore, fpload, fpload, veclogical, vecsimple, vecsimple, vecsimple, veclogical, veclogical, vecsimple, vecsimple, mfjmpr, mtjmpr, *, - mftgpr, mffgpr, mftgpr, mffgpr") + mftgpr, mffgpr") (set_attr "size" "64") (set_attr "length" "4, 4, 4, 4, 4, 20, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, - 4, 4, 4, 4") + 4, 4") (set_attr "isa" "*, *, *, *, *, *, *, *, *, p9v, *, p9v, *, *, p9v, p9v, *, *, *, *, *, *, *, *, - *, *, p8v, p8v")]) + p8v, p8v")]) ; Some DImode loads are best done as a load of -1 followed by a mask ; instruction. diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 4bc57d680af..cf513261d78 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3197,7 +3197,7 @@ Altivec vector register Any VSX register if the @option{-mvsx} option was used or NO_REGS. When using any of the register constraints (@code{wa}, @code{wd}, -@code{wf}, @code{wg}, @code{wi}, +@code{wf}, @code{wi}, @code{wp}, @code{wq}, @code{ws}, @code{wt}, @code{wv}, or @code{ww}) that take VSX registers, you must use @code{%x} in the template so @@ -3256,9 +3256,6 @@ were used or NO_REGS. @item wf VSX vector register to hold vector float data or NO_REGS. -@item wg -If @option{-mmfpgpr} was used, a floating point register or NO_REGS. - @item wi FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS. -- 2.30.2