From ecad3ff45c5b08320c9189b87c7511f1cfacf4c8 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 3 Jul 2022 11:30:33 +0100 Subject: [PATCH] --- openpower/sv.mdwn | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn index 66cb1e370..a669890a3 100644 --- a/openpower/sv.mdwn +++ b/openpower/sv.mdwn @@ -194,7 +194,11 @@ Simple-V itself only requires five instructions with 6-bit Minor XO (bits 26-31), and the SVP64 Prefix Encoding requires 25% space of the EXT001 Major Opcode. There are **no** Vector Instructions and consequently **no further -opcode space is required**. +opcode space is required**. Even though they are currently +placed in the EXT022 Sandbox, the "Management" instructions +(setvl, svstep, svremap, svshape, svindex) are designed to fit +cleanly into EXT019 (like `addpcis`) or other 5/6-bit Minor +XO area. That said: for the target workloads for which Scalable Vectors are typically used, the Scalar ISA on which those workloads critically rely @@ -222,8 +226,6 @@ way critically depends on the 100 or so *Scalar* instructions also being developed by Libre-SOC. Therefore the Opcode summary below is again divided into two: SVP64, then Scalar instructions. -* SVP64 requires 25% of EXT01 (bits 6 and 9 set to 1) - **None of these Draft opcodes are intended for private custom secret proprietary usage. They are all intended for entirely public, upstream, high-profile mass-volume day-to-day usage at the -- 2.30.2