From ecb519165e2a77fef42f8727c6478bf0fd89ebf9 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 29 Jan 2021 00:05:36 +0000 Subject: [PATCH] --- openpower/sv/implementation.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn index 88836a382..ae3205aa9 100644 --- a/openpower/sv/implementation.mdwn +++ b/openpower/sv/implementation.mdwn @@ -109,7 +109,7 @@ SV's SVSTATE context is effectively a Sub-PC. On exceptions the PC is saved int main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1. Register numbers are incremented by one if marked as vector. -*This loop goes in between decode and issue phases*. It is as if there were multiple sequential instructions in the instruction stream *and the loop must be treated as such*. Specifically: all register read and write hazards **MUST** be respected; the Program Order must be respected. +*This loop goes in between decode and issue phases*. It is as if there were multiple sequential instructions in the instruction stream *and the loop must be treated as such*. Specifically: all register read and write hazards **MUST** be respected; the Program Order must be respected even though and especially because this is Sub-PC execution. This **includes** any exceptions, hence why SVSTATE exists and why SVSRR0 must be used to store SVSTATE alongside when SRR0 and SRR1 store PC and MSR. -- 2.30.2