From ecc500398f29c2dd7a86de7dec20f121974c65a2 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Wed, 19 Jun 2019 23:12:52 -0500 Subject: [PATCH] iris: Drop RT flushes from depth stencil clearing flushes. These write depth and stencil, not color writes, so there's no need to flush the render target. --- src/gallium/drivers/iris/iris_blit.c | 2 ++ src/gallium/drivers/iris/iris_clear.c | 5 +++-- src/gallium/drivers/iris/iris_resource.c | 9 ++------- src/gallium/drivers/iris/iris_resource.h | 1 + 4 files changed, 8 insertions(+), 9 deletions(-) diff --git a/src/gallium/drivers/iris/iris_blit.c b/src/gallium/drivers/iris/iris_blit.c index 1ac56aa4eaf..6f90910b516 100644 --- a/src/gallium/drivers/iris/iris_blit.c +++ b/src/gallium/drivers/iris/iris_blit.c @@ -493,6 +493,7 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) iris_flush_and_dirty_for_history(ice, batch, (struct iris_resource *) info->dst.resource, + PIPE_CONTROL_RENDER_TARGET_FLUSH, "cache history: post-blit"); } @@ -640,6 +641,7 @@ iris_resource_copy_region(struct pipe_context *ctx, } iris_flush_and_dirty_for_history(ice, batch, (struct iris_resource *) dst, + PIPE_CONTROL_RENDER_TARGET_FLUSH, "cache history: post copy_region"); } diff --git a/src/gallium/drivers/iris/iris_clear.c b/src/gallium/drivers/iris/iris_clear.c index 23348077d31..1724a35c54e 100644 --- a/src/gallium/drivers/iris/iris_clear.c +++ b/src/gallium/drivers/iris/iris_clear.c @@ -349,6 +349,7 @@ clear_color(struct iris_context *ice, blorp_batch_finish(&blorp_batch); iris_flush_and_dirty_for_history(ice, batch, res, + PIPE_CONTROL_RENDER_TARGET_FLUSH, "cache history: post color clear"); iris_resource_finish_render(ice, res, level, @@ -515,7 +516,7 @@ clear_depth_stencil(struct iris_context *ice, if (z_res && clear_depth && can_fast_clear_depth(ice, z_res, level, box, depth)) { fast_clear_depth(ice, z_res, level, box, depth); - iris_flush_and_dirty_for_history(ice, batch, res, + iris_flush_and_dirty_for_history(ice, batch, res, 0, "cache history: post fast Z clear"); clear_depth = false; z_res = false; @@ -552,7 +553,7 @@ clear_depth_stencil(struct iris_context *ice, clear_stencil && stencil_res ? 0xff : 0, stencil); blorp_batch_finish(&blorp_batch); - iris_flush_and_dirty_for_history(ice, batch, res, + iris_flush_and_dirty_for_history(ice, batch, res, 0, "cache history: post slow ZS clear"); if (z_res) { diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c index 8ca1e6e940a..9a2b7bda22b 100644 --- a/src/gallium/drivers/iris/iris_resource.c +++ b/src/gallium/drivers/iris/iris_resource.c @@ -1572,18 +1572,13 @@ void iris_flush_and_dirty_for_history(struct iris_context *ice, struct iris_batch *batch, struct iris_resource *res, + uint32_t extra_flags, const char *reason) { if (res->base.target != PIPE_BUFFER) return; - uint32_t flush = iris_flush_bits_for_history(res); - - /* We've likely used the rendering engine (i.e. BLORP) to write to this - * surface. Flush the render cache so the data actually lands. - */ - if (batch->name != IRIS_BATCH_COMPUTE) - flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH; + uint32_t flush = iris_flush_bits_for_history(res) | extra_flags; iris_emit_pipe_control_flush(batch, reason, flush); diff --git a/src/gallium/drivers/iris/iris_resource.h b/src/gallium/drivers/iris/iris_resource.h index 419122c8bbd..75f04d492d9 100644 --- a/src/gallium/drivers/iris/iris_resource.h +++ b/src/gallium/drivers/iris/iris_resource.h @@ -268,6 +268,7 @@ uint32_t iris_flush_bits_for_history(struct iris_resource *res); void iris_flush_and_dirty_for_history(struct iris_context *ice, struct iris_batch *batch, struct iris_resource *res, + uint32_t extra_flags, const char *reason); unsigned iris_get_num_logical_layers(const struct iris_resource *res, -- 2.30.2