From ece423415cbc17654c6ac81a0f4b15783c558660 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Dec 2019 14:24:58 -0800 Subject: [PATCH] Add CHANGELOG entry, add abc9_{flop,keep} attr to README.md --- CHANGELOG | 1 + README.md | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/CHANGELOG b/CHANGELOG index 01ae17c2b..fc0cdc92e 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -57,6 +57,7 @@ Yosys 0.9 .. Yosys 0.9-dev always_latch and always_ff) - Added "xilinx_dffopt" pass - Added "scratchpad" pass + - Added "synth_xilinx -dff" Yosys 0.8 .. Yosys 0.9 ---------------------- diff --git a/README.md b/README.md index 0250c7846..c04e2b9ec 100644 --- a/README.md +++ b/README.md @@ -378,6 +378,12 @@ Verilog Attributes and non-standard features for example, to specify the clk-to-Q delay of a flip-flop for consideration during techmapping. +- The module attribute ``abc9_flop`` is a boolean marking the module as a + whitebox that describes the synchronous behaviour of a flip-flop. + +- The cell attribute ``abc9_keep`` is a boolean indicating that this black/ + white box should be preserved through `abc9` mapping. + - The frontend sets attributes ``always_comb``, ``always_latch`` and ``always_ff`` on processes derived from SystemVerilog style always blocks according to the type of the always. These are checked for correctness in -- 2.30.2