From ecfe1646ec4600a12a5e33da63b7947c1f205b42 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Tue, 12 Mar 2013 16:16:06 +0100
Subject: [PATCH] fhdl/verilog: implicit get_fragment

---
 migen/fhdl/verilog.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index c5ba2272..795fcf00 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -260,6 +260,8 @@ def convert(f, ios=None, name="top",
   return_ns=False,
   special_overrides=dict(),
   display_run=False):
+	if not isinstance(f, Fragment):
+		f = f.get_fragment()
 	if ios is None:
 		ios = set()
 	if clock_domains is None:
-- 
2.30.2