From ed054d04c937dc4b7e20869b25b50cd8bd19e1c8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 19 Sep 2020 14:36:25 +0100 Subject: [PATCH] add (disabled) tri-state GPIO --- src/soc/litex/florent/libresoc/ls180.py | 11 +++++++++++ src/soc/litex/florent/ls180soc.py | 6 +++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py index 5b392ef8..c77644ba 100644 --- a/src/soc/litex/florent/libresoc/ls180.py +++ b/src/soc/litex/florent/libresoc/ls180.py @@ -73,6 +73,17 @@ _io = [ ] +if False: + pinbank1 = [] + pinbank2 = [] + for i in range(8): + pinbank1.append("X%d" % i) + pinbank2.append("Y%d" % i) + pins = ' '.join(pinbank1 + pinbank2) + + # 16 GPIOs + _io.append( ("gpio", 16, Pins(pins), IOStandard("LVCMOS33")) ) + pinsin = [] pinsout = [] for i in range(8): diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py index 67f87fde..66d1864d 100755 --- a/src/soc/litex/florent/ls180soc.py +++ b/src/soc/litex/florent/ls180soc.py @@ -20,7 +20,7 @@ from litedram import modules as litedram_modules from litedram.phy.model import SDRAMPHYModel from litedram.phy.gensdrphy import GENSDRPHY, HalfRateGENSDRPHY -from litex.soc.cores.gpio import GPIOInOut, GPIOIn, GPIOOut +from litex.soc.cores.gpio import GPIOInOut, GPIOIn, GPIOOut, GPIOTristate from litex.soc.cores.spi import SPIMaster from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings @@ -189,6 +189,10 @@ class LibreSoCSim(SoCCore): self.submodules.gpio_out = GPIOIn(platform.request("gpio_out")) self.add_csr("gpio_out") + if False: + self.submodules.gpio = GPIOTristate(platform.request("gpio")) + self.add_csr("gpio") + # SPI Master self.submodules.spi_master = SPIMaster( pads = platform.request("spi_master"), -- 2.30.2