From ed429b33c1ee8d6d8f8e640e58f04ec800bc7b2a Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 30 Mar 2023 11:09:13 +0100 Subject: [PATCH] aarch64: Add the SME2 MLAL and MLSL instructions The {BF,F,S,U}MLAL and {BF,F,S,U}MLSL instructions share the same encoding. They are the first instance of a ZA (as opposed to ZA tile) operand having a range of offsets. As with ZA tiles, the expected range size is encoded in the operand-specific data field. --- gas/config/tc-aarch64.c | 4 + gas/testsuite/gas/aarch64/sme2-12-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-12-invalid.l | 155 ++ gas/testsuite/gas/aarch64/sme2-12-invalid.s | 136 ++ gas/testsuite/gas/aarch64/sme2-12-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-12-noarch.l | 571 ++++++ gas/testsuite/gas/aarch64/sme2-12.d | 579 ++++++ gas/testsuite/gas/aarch64/sme2-12.s | 633 ++++++ include/opcode/aarch64.h | 4 + opcodes/aarch64-asm-2.c | 36 +- opcodes/aarch64-asm.c | 4 +- opcodes/aarch64-dis-2.c | 2026 +++++++++++++------ opcodes/aarch64-dis.c | 8 +- opcodes/aarch64-opc-2.c | 4 + opcodes/aarch64-opc.c | 21 + opcodes/aarch64-opc.h | 3 + opcodes/aarch64-tbl.h | 74 + 17 files changed, 3586 insertions(+), 678 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sme2-12-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-12-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-12-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-12-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-12-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-12.d create mode 100644 gas/testsuite/gas/aarch64/sme2-12.s diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 47ad7048372..2aa38381f47 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6729,6 +6729,8 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Zn_INDEX: case AARCH64_OPND_SME_Zm_INDEX1: case AARCH64_OPND_SME_Zm_INDEX2: + case AARCH64_OPND_SME_Zm_INDEX3_2: + case AARCH64_OPND_SME_Zm_INDEX3_10: case AARCH64_OPND_SME_Zn_INDEX1_16: case AARCH64_OPND_SME_Zn_INDEX2_15: case AARCH64_OPND_SME_Zn_INDEX2_16: @@ -7850,8 +7852,10 @@ parse_operands (char *str, const aarch64_opcode *opcode) info->imm.value = val; break; + case AARCH64_OPND_SME_ZA_array_off2x2: case AARCH64_OPND_SME_ZA_array_off3_0: case AARCH64_OPND_SME_ZA_array_off3_5: + case AARCH64_OPND_SME_ZA_array_off3x2: case AARCH64_OPND_SME_ZA_array_off4: if (!parse_dual_indexed_reg (&str, REG_TYPE_ZA, &info->indexed_za, &qualifier, 0)) diff --git a/gas/testsuite/gas/aarch64/sme2-12-invalid.d b/gas/testsuite/gas/aarch64/sme2-12-invalid.d new file mode 100644 index 00000000000..2ce41523b0f --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-12-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-12-invalid.s +#error_output: sme2-12-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-12-invalid.l b/gas/testsuite/gas/aarch64/sme2-12-invalid.l new file mode 100644 index 00000000000..a387bb73806 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-12-invalid.l @@ -0,0 +1,155 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a ZA array vector at operand 1 -- `bfmlal 0,z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 2 -- `bfmlal za\.s\[w8,0:1\],0,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bfmlal za\.s\[w8,0:1\],z0\.h,0' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w7,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w12,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `bfmlal za\.s\[w8,0\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `bfmlal za\.s\[w8,0:0\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `bfmlal za\.s\[w8,0:2\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `bfmlal za\.s\[w8,1:2\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `bfmlal za\.s\[w8,1:0\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `bfmlal za\.s\[w8,-2:-1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `bfmlal za\.s\[w8,16:17\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: unexpected vector group size at operand 1 -- `bfmlal za\.s\[w8,0:1,vgx2\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `bfmlal za\.s\[w8,0:1\],z0\.h,z16\.h\[0\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlal za\.s\[w8,0:1\],z0\.h,z0\.h\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlal za\.s\[w8,0:1\],z0\.h,z0\.h\[8\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlal za\.s\[w8,0:1\],z0\.s,z0\.s\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlal za\.s\[w8, 0:1\], z0\.h, z0\.h\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlal za\.h\[w8,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlal za\.s\[w8, 0:1\], z0\.h, z0\.h\[0\] +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w7,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w12,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `bfmlal za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `bfmlal za\.s\[w8,0:0\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `bfmlal za\.s\[w8,0:2\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `bfmlal za\.s\[w8,1:2\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `bfmlal za\.s\[w8,1:0\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,-2:-1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,8:9\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,16:17\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `bfmlal za\.s\[w8,0:1,vgx4\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `bfmlal za\.s\[w8,0:1\],{z1\.h-z2\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `bfmlal za\.s\[w8,0:1\],{z1\.h,z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z16\.h\[0\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[8\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlal za\.s\[w8,0:1\],{z0\.s-z1\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlal za\.s\[w8, 0:1\], {z0\.h-z1\.h}, z0\.h\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlal za\.h\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlal za\.s\[w8, 0:1\], {z0\.h-z1\.h}, z0\.h\[0\] +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w7,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w12,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `bfmlal za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `bfmlal za\.s\[w8,0:0\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `bfmlal za\.s\[w8,0:2\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `bfmlal za\.s\[w8,1:2\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `bfmlal za\.s\[w8,1:0\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,-2:-1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,8:9\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,16:17\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `bfmlal za\.s\[w8,0:1,vgx2\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `bfmlal za\.s\[w8,0:1\],{z1\.h-z4\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `bfmlal za\.s\[w8,0:1\],{z1\.h,z3\.h,z5\.h,z7\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z16\.h\[0\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[8\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlal za\.s\[w8,0:1\],{z0\.s-z3\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlal za\.s\[w8, 0:1\], {z0\.h-z3\.h}, z0\.h\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlal za\.h\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlal za\.s\[w8, 0:1\], {z0\.h-z3\.h}, z0\.h\[0\] +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w7,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w12,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `bfmlal za\.s\[w8,0\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `bfmlal za\.s\[w8,0:0\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `bfmlal za\.s\[w8,0:2\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `bfmlal za\.s\[w8,1:2\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `bfmlal za\.s\[w8,1:0\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `bfmlal za\.s\[w8,-2:-1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `bfmlal za\.s\[w8,16:17\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: unexpected vector group size at operand 1 -- `bfmlal za\.s\[w8,0:1,vgx2\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `bfmlal za\.s\[w8,0:1\],z0\.h,z16\.h' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlal za\.s\[w8,0:1\],z0\.s,z0\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlal za\.s\[w8, 0:1\], z0\.h, z0\.h +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlal za\.h\[w8,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlal za\.s\[w8, 0:1\], z0\.h, z0\.h +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w7,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w12,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `bfmlal za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `bfmlal za\.s\[w8,0:0\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `bfmlal za\.s\[w8,0:2\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `bfmlal za\.s\[w8,1:2\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `bfmlal za\.s\[w8,1:0\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,-2:-1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,8:9\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,16:17\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `bfmlal za\.s\[w8,0:1,vgx4\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `bfmlal za\.s\[w8,0:1\],{z1\.h,z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z16\.h' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlal za\.s\[w8,0:1\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlal za\.s\[w8, 0:1\], {z0\.h-z1\.h}, z0\.h +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlal za\.h\[w8,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlal za\.s\[w8, 0:1\], {z0\.h-z1\.h}, z0\.h +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w7,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w12,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `bfmlal za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `bfmlal za\.s\[w8,0:0\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `bfmlal za\.s\[w8,0:2\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `bfmlal za\.s\[w8,1:2\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `bfmlal za\.s\[w8,1:0\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,-2:-1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,8:9\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,16:17\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `bfmlal za\.s\[w8,0:1,vgx2\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `bfmlal za\.s\[w8,0:1\],{z1\.h,z3\.h,z5\.h,z7\.h},z0\.h' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z16\.h' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlal za\.s\[w8,0:1\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlal za\.s\[w8, 0:1\], {z0\.h-z3\.h}, z0\.h +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlal za\.h\[w8,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlal za\.s\[w8, 0:1\], {z0\.h-z3\.h}, z0\.h +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w7,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w12,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,-2:-1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `bfmlal za\.s\[w8,1:2\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,8:9\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `bfmlal za\.s\[w8,0:1\],{z1\.h-z2\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},{z15\.h-z16\.h}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},{z31\.h,z0\.h}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w7,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `bfmlal za\.s\[w12,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,-2:-1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `bfmlal za\.s\[w8,1:2\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `bfmlal za\.s\[w8,8:9\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `bfmlal za\.s\[w8,0:1\],{z1\.h-z4\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `bfmlal za\.s\[w8,0:1\],{z2\.h-z5\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `bfmlal za\.s\[w8,0:1\],{z3\.h-z6\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},{z15\.h-z18\.h}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},{z29\.h,z30\.h,z31\.h,z0\.h}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z2\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},{z0\.h-z2\.h}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},{z0\.h-z4\.h}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `bfmlal za\.s\[w8,0:1,vgx4\],{z0\.h-z1\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `bfmlal za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `bfmlal za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `bfmlal za\.s\[w8,0:1,vgx2\],{z0\.h-z3\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlal za\[w8,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlal za\.s\[w8, 0:1\], {z0\.h-z1\.h}, {z0\.h-z1\.h} +[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlal za\[w8,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: bfmlal za\.s\[w8, 0:1\], {z0\.h-z3\.h}, {z0\.h-z3\.h} diff --git a/gas/testsuite/gas/aarch64/sme2-12-invalid.s b/gas/testsuite/gas/aarch64/sme2-12-invalid.s new file mode 100644 index 00000000000..1d158ed6912 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-12-invalid.s @@ -0,0 +1,136 @@ + bfmlal 0, z0.h, z0.h[0] + bfmlal za.s[w8, 0:1], 0, z0.h[0] + bfmlal za.s[w8, 0:1], z0.h, 0 + + bfmlal za.s[w7, 0:1], z0.h, z0.h[0] + bfmlal za.s[w12, 0:1], z0.h, z0.h[0] + bfmlal za.s[w8, 0], z0.h, z0.h[0] + bfmlal za.s[w8, 0:0], z0.h, z0.h[0] + bfmlal za.s[w8, 0:2], z0.h, z0.h[0] + bfmlal za.s[w8, 1:2], z0.h, z0.h[0] + bfmlal za.s[w8, 1:0], z0.h, z0.h[0] + bfmlal za.s[w8, -2:-1], z0.h, z0.h[0] + bfmlal za.s[w8, 16:17], z0.h, z0.h[0] + bfmlal za.s[w8, 0:1, vgx2], z0.h, z0.h[0] + bfmlal za.s[w8, 0:1], z0.h, z16.h[0] + bfmlal za.s[w8, 0:1], z0.h, z0.h[-1] + bfmlal za.s[w8, 0:1], z0.h, z0.h[8] + bfmlal za.s[w8, 0:1], z0.s, z0.s[0] + bfmlal za.h[w8, 0:1], z0.h, z0.h[0] + + bfmlal za.s[w7, 0:1], { z0.h - z1.h }, z0.h[0] + bfmlal za.s[w12, 0:1], { z0.h - z1.h }, z0.h[0] + bfmlal za.s[w8, 0], { z0.h - z1.h }, z0.h[0] + bfmlal za.s[w8, 0:0], { z0.h - z1.h }, z0.h[0] + bfmlal za.s[w8, 0:2], { z0.h - z1.h }, z0.h[0] + bfmlal za.s[w8, 1:2], { z0.h - z1.h }, z0.h[0] + bfmlal za.s[w8, 1:0], { z0.h - z1.h }, z0.h[0] + bfmlal za.s[w8, -2:-1], { z0.h - z1.h }, z0.h[0] + bfmlal za.s[w8, 8:9], { z0.h - z1.h }, z0.h[0] + bfmlal za.s[w8, 16:17], { z0.h - z1.h }, z0.h[0] + bfmlal za.s[w8, 0:1, vgx4], { z0.h - z1.h }, z0.h[0] + bfmlal za.s[w8, 0:1], { z1.h - z2.h }, z0.h[0] + bfmlal za.s[w8, 0:1], { z1.h, z3.h }, z0.h[0] + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, z16.h[0] + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, z0.h[-1] + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, z0.h[8] + bfmlal za.s[w8, 0:1], { z0.s - z1.s }, z0.s[0] + bfmlal za.h[w8, 0:1], { z0.h - z1.h }, z0.h[0] + + bfmlal za.s[w7, 0:1], { z0.h - z3.h }, z0.h[0] + bfmlal za.s[w12, 0:1], { z0.h - z3.h }, z0.h[0] + bfmlal za.s[w8, 0], { z0.h - z3.h }, z0.h[0] + bfmlal za.s[w8, 0:0], { z0.h - z3.h }, z0.h[0] + bfmlal za.s[w8, 0:2], { z0.h - z3.h }, z0.h[0] + bfmlal za.s[w8, 1:2], { z0.h - z3.h }, z0.h[0] + bfmlal za.s[w8, 1:0], { z0.h - z3.h }, z0.h[0] + bfmlal za.s[w8, -2:-1], { z0.h - z3.h }, z0.h[0] + bfmlal za.s[w8, 8:9], { z0.h - z3.h }, z0.h[0] + bfmlal za.s[w8, 16:17], { z0.h - z3.h }, z0.h[0] + bfmlal za.s[w8, 0:1, vgx2], { z0.h - z3.h }, z0.h[0] + bfmlal za.s[w8, 0:1], { z1.h - z4.h }, z0.h[0] + bfmlal za.s[w8, 0:1], { z1.h, z3.h, z5.h, z7.h }, z0.h[0] + bfmlal za.s[w8, 0:1], { z0.h - z3.h }, z16.h[0] + bfmlal za.s[w8, 0:1], { z0.h - z3.h }, z0.h[-1] + bfmlal za.s[w8, 0:1], { z0.h - z3.h }, z0.h[8] + bfmlal za.s[w8, 0:1], { z0.s - z3.s }, z0.s[0] + bfmlal za.h[w8, 0:1], { z0.h - z3.h }, z0.h[0] + + bfmlal za.s[w7, 0:1], z0.h, z0.h + bfmlal za.s[w12, 0:1], z0.h, z0.h + bfmlal za.s[w8, 0], z0.h, z0.h + bfmlal za.s[w8, 0:0], z0.h, z0.h + bfmlal za.s[w8, 0:2], z0.h, z0.h + bfmlal za.s[w8, 1:2], z0.h, z0.h + bfmlal za.s[w8, 1:0], z0.h, z0.h + bfmlal za.s[w8, -2:-1], z0.h, z0.h + bfmlal za.s[w8, 16:17], z0.h, z0.h + bfmlal za.s[w8, 0:1, vgx2], z0.h, z0.h + bfmlal za.s[w8, 0:1], z0.h, z16.h + bfmlal za.s[w8, 0:1], z0.s, z0.s + bfmlal za.h[w8, 0:1], z0.h, z0.h + + bfmlal za.s[w7, 0:1], { z0.h - z1.h }, z0.h + bfmlal za.s[w12, 0:1], { z0.h - z1.h }, z0.h + bfmlal za.s[w8, 0], { z0.h - z1.h }, z0.h + bfmlal za.s[w8, 0:0], { z0.h - z1.h }, z0.h + bfmlal za.s[w8, 0:2], { z0.h - z1.h }, z0.h + bfmlal za.s[w8, 1:2], { z0.h - z1.h }, z0.h + bfmlal za.s[w8, 1:0], { z0.h - z1.h }, z0.h + bfmlal za.s[w8, -2:-1], { z0.h - z1.h }, z0.h + bfmlal za.s[w8, 8:9], { z0.h - z1.h }, z0.h + bfmlal za.s[w8, 16:17], { z0.h - z1.h }, z0.h + bfmlal za.s[w8, 0:1, vgx4], { z0.h - z1.h }, z0.h + bfmlal za.s[w8, 0:1], { z1.h, z3.h }, z0.h + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, z16.h + bfmlal za.s[w8, 0:1], { z0.s - z1.s }, z0.s + bfmlal za.h[w8, 0:1], { z0.h - z1.h }, z0.h + + bfmlal za.s[w7, 0:1], { z0.h - z3.h }, z0.h + bfmlal za.s[w12, 0:1], { z0.h - z3.h }, z0.h + bfmlal za.s[w8, 0], { z0.h - z3.h }, z0.h + bfmlal za.s[w8, 0:0], { z0.h - z3.h }, z0.h + bfmlal za.s[w8, 0:2], { z0.h - z3.h }, z0.h + bfmlal za.s[w8, 1:2], { z0.h - z3.h }, z0.h + bfmlal za.s[w8, 1:0], { z0.h - z3.h }, z0.h + bfmlal za.s[w8, -2:-1], { z0.h - z3.h }, z0.h + bfmlal za.s[w8, 8:9], { z0.h - z3.h }, z0.h + bfmlal za.s[w8, 16:17], { z0.h - z3.h }, z0.h + bfmlal za.s[w8, 0:1, vgx2], { z0.h - z3.h }, z0.h + bfmlal za.s[w8, 0:1], { z1.h, z3.h, z5.h, z7.h }, z0.h + bfmlal za.s[w8, 0:1], { z0.h - z3.h }, z16.h + bfmlal za.s[w8, 0:1], { z0.s - z3.s }, z0.s + bfmlal za.h[w8, 0:1], { z0.h - z3.h }, z0.h + + bfmlal za.s[w7, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + bfmlal za.s[w12, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + bfmlal za.s[w8, -2:-1], { z0.h - z1.h }, { z0.h - z1.h } + bfmlal za.s[w8, 1:2], { z0.h - z1.h }, { z0.h - z1.h } + bfmlal za.s[w8, 8:9], { z0.h - z1.h }, { z0.h - z1.h } + bfmlal za.s[w8, 0:1], { z1.h - z2.h }, { z0.h - z1.h } + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, { z15.h - z16.h } + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, { z31.h, z0.h } + + bfmlal za.s[w7, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + bfmlal za.s[w12, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + bfmlal za.s[w8, -2:-1], { z0.h - z3.h }, { z0.h - z3.h } + bfmlal za.s[w8, 1:2], { z0.h - z3.h }, { z0.h - z3.h } + bfmlal za.s[w8, 8:9], { z0.h - z3.h }, { z0.h - z3.h } + bfmlal za.s[w8, 0:1], { z1.h - z4.h }, { z0.h - z3.h } + bfmlal za.s[w8, 0:1], { z2.h - z5.h }, { z0.h - z3.h } + bfmlal za.s[w8, 0:1], { z3.h - z6.h }, { z0.h - z3.h } + bfmlal za.s[w8, 0:1], { z0.h - z3.h }, { z15.h - z18.h } + bfmlal za.s[w8, 0:1], { z0.h - z3.h }, { z29.h, z30.h, z31.h, z0.h } + + bfmlal za.s[w8, 0:1], { z0.h - z2.h }, { z0.h - z1.h } + bfmlal za.s[w8, 0:1], { z0.h - z3.h }, { z0.h - z1.h } + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, { z0.h - z2.h } + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, { z0.h - z3.h } + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, { z0.h - z4.h } + + bfmlal za.s[w8, 0:1, vgx4], { z0.h - z1.h }, { z0.h - z3.h } + bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z1.h } + bfmlal za.s[w8, 0:1, vgx2], { z0.h - z1.h }, { z0.h - z3.h } + bfmlal za.s[w8, 0:1, vgx2], { z0.h - z3.h }, { z0.h - z1.h } + bfmlal za[w8, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + bfmlal za[w8, 0:1], { z0.h - z3.h }, { z0.h - z3.h } diff --git a/gas/testsuite/gas/aarch64/sme2-12-noarch.d b/gas/testsuite/gas/aarch64/sme2-12-noarch.d new file mode 100644 index 00000000000..ecaeede5221 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-12-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme2-12.s +#error_output: sme2-12-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-12-noarch.l b/gas/testsuite/gas/aarch64/sme2-12-noarch.l new file mode 100644 index 00000000000..7544d1e2164 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-12-noarch.l @@ -0,0 +1,571 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.s\[W8,0:1\],Z0\.h,Z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.S\[W8,0:1\],Z0\.H,Z0\.H\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w11,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,14:15\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],z31\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],z0\.h,z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],z0\.h,z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w9,10:11\],z21\.h,z9\.h\[2\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.s\[W8,0:1,VGx2\],{Z0\.h-Z1\.h},Z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.S\[W8,0:1,VGX2\],{Z0\.H-Z1\.H},Z0\.H\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w9,4:5\],{z18\.h-z19\.h},z9\.h\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.s\[W8,0:1,VGx4\],{Z0\.h-Z3\.h},Z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.S\[W8,0:1,VGX4\],{Z0\.H-Z3\.H},Z0\.H\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w9,4:5\],{z24\.h-z27\.h},z14\.h\[5\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.s\[W8,0:1\],Z0\.h,Z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.S\[W8,0:1\],Z0\.H,Z0\.H' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w11,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,14:15\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],z31\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],z0\.h,z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w10,2:3\],z25\.h,z7\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.s\[W8,0:1,VGx2\],{Z0\.h-Z1\.h},Z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.S\[W8,0:1,VGX2\],{Z0\.H-Z1\.H},Z0\.H' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z1\.h-z2\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z31\.h,z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z31\.h-z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w9,4:5\],{z18\.h-z19\.h},z13\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.s\[W8,0:1,VGx4\],{Z0\.h-Z3\.h},Z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.S\[W8,0:1,VGX4\],{Z0\.H-Z3\.H},Z0\.H' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w11,0:1\],{z1\.h-z4\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z29\.h,z30\.h,z31\.h,z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z29\.h-z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z30\.h,z31\.h,z0\.h,z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z30\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z31\.h,z0\.h,z1\.h,z2\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z31\.h-z2\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w9,4:5\],{z24\.h-z27\.h},z14\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.s\[W8,0:1,VGx2\],{Z0\.h-Z1\.h},{Z0\.h-Z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.S\[W8,0:1,VGX2\],{Z0\.H-Z1\.H},{Z0\.H-Z1\.H}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w11,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,6:7\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z30\.h-z31\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},{z30\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w10,2:3\],{z22\.h-z23\.h},{z18\.h-z19\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.s\[W8,0:1,VGx4\],{Z0\.h-Z3\.h},{Z0\.h-Z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal ZA\.S\[W8,0:1,VGX4\],{Z0\.H-Z3\.H},{Z0\.H-Z3\.H}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w11,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,6:7\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z28\.h-z31\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},{z28\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlal za\.s\[w11,4:5\],{z16\.h-z19\.h},{z24\.h-z27\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.s\[W8,0:1\],Z0\.h,Z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.S\[W8,0:1\],Z0\.H,Z0\.H\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w11,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,14:15\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],z31\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],z0\.h,z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],z0\.h,z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w9,10:11\],z21\.h,z9\.h\[2\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.s\[W8,0:1,VGx2\],{Z0\.h-Z1\.h},Z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.S\[W8,0:1,VGX2\],{Z0\.H-Z1\.H},Z0\.H\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w9,4:5\],{z18\.h-z19\.h},z9\.h\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.s\[W8,0:1,VGx4\],{Z0\.h-Z3\.h},Z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.S\[W8,0:1,VGX4\],{Z0\.H-Z3\.H},Z0\.H\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w9,4:5\],{z24\.h-z27\.h},z14\.h\[5\]' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.s\[W8,0:1\],Z0\.h,Z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.S\[W8,0:1\],Z0\.H,Z0\.H' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w11,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,14:15\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],z31\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],z0\.h,z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w10,2:3\],z25\.h,z7\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.s\[W8,0:1,VGx2\],{Z0\.h-Z1\.h},Z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.S\[W8,0:1,VGX2\],{Z0\.H-Z1\.H},Z0\.H' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w9,4:5\],{z18\.h-z19\.h},z13\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.s\[W8,0:1,VGx4\],{Z0\.h-Z3\.h},Z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.S\[W8,0:1,VGX4\],{Z0\.H-Z3\.H},Z0\.H' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w9,4:5\],{z24\.h-z27\.h},z14\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.s\[W8,0:1,VGx2\],{Z0\.h-Z1\.h},{Z0\.h-Z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.S\[W8,0:1,VGX2\],{Z0\.H-Z1\.H},{Z0\.H-Z1\.H}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w11,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,6:7\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z30\.h-z31\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},{z30\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w10,2:3\],{z22\.h-z23\.h},{z18\.h-z19\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.s\[W8,0:1,VGx4\],{Z0\.h-Z3\.h},{Z0\.h-Z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl ZA\.S\[W8,0:1,VGX4\],{Z0\.H-Z3\.H},{Z0\.H-Z3\.H}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w11,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,6:7\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z28\.h-z31\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},{z28\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `bfmlsl za\.s\[w11,4:5\],{z16\.h-z19\.h},{z24\.h-z27\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.s\[W8,0:1\],Z0\.h,Z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.S\[W8,0:1\],Z0\.H,Z0\.H\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w11,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,14:15\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],z31\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],z0\.h,z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],z0\.h,z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w9,10:11\],z21\.h,z9\.h\[2\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.s\[W8,0:1,VGx2\],{Z0\.h-Z1\.h},Z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.S\[W8,0:1,VGX2\],{Z0\.H-Z1\.H},Z0\.H\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w9,4:5\],{z18\.h-z19\.h},z9\.h\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.s\[W8,0:1,VGx4\],{Z0\.h-Z3\.h},Z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.S\[W8,0:1,VGX4\],{Z0\.H-Z3\.H},Z0\.H\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w9,4:5\],{z24\.h-z27\.h},z14\.h\[5\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.s\[W8,0:1\],Z0\.h,Z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.S\[W8,0:1\],Z0\.H,Z0\.H' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w11,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,14:15\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],z31\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],z0\.h,z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w10,2:3\],z25\.h,z7\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.s\[W8,0:1,VGx2\],{Z0\.h-Z1\.h},Z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.S\[W8,0:1,VGX2\],{Z0\.H-Z1\.H},Z0\.H' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z31\.h,z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z31\.h-z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w9,4:5\],{z19\.h-z20\.h},z13\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.s\[W8,0:1,VGx4\],{Z0\.h-Z3\.h},Z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.S\[W8,0:1,VGX4\],{Z0\.H-Z3\.H},Z0\.H' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z29\.h-z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z30\.h,z31\.h,z0\.h,z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z30\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z31\.h-z2\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w9,4:5\],{z25\.h-z28\.h},z14\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.s\[W8,0:1,VGx2\],{Z0\.h-Z1\.h},{Z0\.h-Z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.S\[W8,0:1,VGX2\],{Z0\.H-Z1\.H},{Z0\.H-Z1\.H}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w11,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,6:7\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z30\.h-z31\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z0\.h-z1\.h},{z30\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w10,2:3\],{z22\.h-z23\.h},{z18\.h-z19\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.s\[W8,0:1,VGx4\],{Z0\.h-Z3\.h},{Z0\.h-Z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal ZA\.S\[W8,0:1,VGX4\],{Z0\.H-Z3\.H},{Z0\.H-Z3\.H}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w11,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,6:7\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z28\.h-z31\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w8,0:1\],{z0\.h-z3\.h},{z28\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlal za\.s\[w11,4:5\],{z16\.h-z19\.h},{z24\.h-z27\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.s\[W8,0:1\],Z0\.h,Z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.S\[W8,0:1\],Z0\.H,Z0\.H\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w11,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,14:15\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],z31\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],z0\.h,z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],z0\.h,z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w9,10:11\],z21\.h,z9\.h\[2\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.s\[W8,0:1,VGx2\],{Z0\.h-Z1\.h},Z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.S\[W8,0:1,VGX2\],{Z0\.H-Z1\.H},Z0\.H\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w9,4:5\],{z18\.h-z19\.h},z9\.h\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.s\[W8,0:1,VGx4\],{Z0\.h-Z3\.h},Z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.S\[W8,0:1,VGX4\],{Z0\.H-Z3\.H},Z0\.H\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w9,4:5\],{z24\.h-z27\.h},z14\.h\[5\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.s\[W8,0:1\],Z0\.h,Z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.S\[W8,0:1\],Z0\.H,Z0\.H' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w11,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,14:15\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],z31\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],z0\.h,z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w10,2:3\],z25\.h,z7\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.s\[W8,0:1,VGx2\],{Z0\.h-Z1\.h},Z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.S\[W8,0:1,VGX2\],{Z0\.H-Z1\.H},Z0\.H' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z31\.h,z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z31\.h-z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w9,4:5\],{z19\.h-z20\.h},z13\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.s\[W8,0:1,VGx4\],{Z0\.h-Z3\.h},Z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.S\[W8,0:1,VGX4\],{Z0\.H-Z3\.H},Z0\.H' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z29\.h-z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z30\.h,z31\.h,z0\.h,z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z30\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z31\.h-z2\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w9,4:5\],{z25\.h-z28\.h},z14\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.s\[W8,0:1,VGx2\],{Z0\.h-Z1\.h},{Z0\.h-Z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.S\[W8,0:1,VGX2\],{Z0\.H-Z1\.H},{Z0\.H-Z1\.H}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w11,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,6:7\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z30\.h-z31\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},{z30\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w10,2:3\],{z22\.h-z23\.h},{z18\.h-z19\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.s\[W8,0:1,VGx4\],{Z0\.h-Z3\.h},{Z0\.h-Z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl ZA\.S\[W8,0:1,VGX4\],{Z0\.H-Z3\.H},{Z0\.H-Z3\.H}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w11,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,6:7\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z28\.h-z31\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},{z28\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmlsl za\.s\[w11,4:5\],{z16\.h-z19\.h},{z24\.h-z27\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w11,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,14:15\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],z31\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],z0\.h,z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],z0\.h,z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w9,10:11\],z21\.h,z9\.h\[2\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w9,4:5\],{z18\.h-z19\.h},z9\.h\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w9,4:5\],{z24\.h-z27\.h},z14\.h\[5\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w11,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,14:15\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],z31\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],z0\.h,z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w10,2:3\],z25\.h,z7\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z31\.h,z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z31\.h-z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w9,4:5\],{z19\.h-z20\.h},z13\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z29\.h-z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z30\.h,z31\.h,z0\.h,z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z30\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z31\.h,z0\.h,z1\.h,z2\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z31\.h-z2\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w9,4:5\],{z25\.h-z28\.h},z14\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w11,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,6:7\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z30\.h-z31\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z0\.h-z1\.h},{z30\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w10,2:3\],{z22\.h-z23\.h},{z18\.h-z19\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w11,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,6:7\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z28\.h-z31\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w8,0:1\],{z0\.h-z3\.h},{z28\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlal za\.s\[w11,4:5\],{z16\.h-z19\.h},{z24\.h-z27\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w11,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,14:15\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],z31\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],z0\.h,z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],z0\.h,z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w9,10:11\],z21\.h,z9\.h\[2\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w9,4:5\],{z18\.h-z19\.h},z9\.h\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w9,4:5\],{z24\.h-z27\.h},z14\.h\[5\]' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w11,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,14:15\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],z31\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],z0\.h,z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w10,2:3\],z25\.h,z7\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z31\.h,z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z31\.h-z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w9,4:5\],{z19\.h-z20\.h},z13\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z29\.h-z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z30\.h,z31\.h,z0\.h,z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z30\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z31\.h,z0\.h,z1\.h,z2\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z31\.h-z2\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w9,4:5\],{z25\.h-z28\.h},z14\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w11,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,6:7\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z30\.h-z31\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},{z30\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w10,2:3\],{z22\.h-z23\.h},{z18\.h-z19\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w11,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,6:7\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z28\.h-z31\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},{z28\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `smlsl za\.s\[w11,4:5\],{z16\.h-z19\.h},{z24\.h-z27\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w11,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,14:15\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],z31\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],z0\.h,z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],z0\.h,z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w9,10:11\],z21\.h,z9\.h\[2\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w9,4:5\],{z18\.h-z19\.h},z9\.h\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w9,4:5\],{z24\.h-z27\.h},z14\.h\[5\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w11,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,14:15\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],z31\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],z0\.h,z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w10,2:3\],z25\.h,z7\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z31\.h,z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z31\.h-z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w9,4:5\],{z19\.h-z20\.h},z13\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z29\.h-z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z30\.h,z31\.h,z0\.h,z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z30\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z31\.h,z0\.h,z1\.h,z2\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z31\.h-z2\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w9,4:5\],{z25\.h-z28\.h},z14\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w11,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,6:7\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z30\.h-z31\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z0\.h-z1\.h},{z30\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w10,2:3\],{z22\.h-z23\.h},{z18\.h-z19\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w11,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,6:7\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z28\.h-z31\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w8,0:1\],{z0\.h-z3\.h},{z28\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlal za\.s\[w11,4:5\],{z16\.h-z19\.h},{z24\.h-z27\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w11,0:1\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,14:15\],z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],z31\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],z0\.h,z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],z0\.h,z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w9,10:11\],z21\.h,z9\.h\[2\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w9,4:5\],{z18\.h-z19\.h},z9\.h\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w9,4:5\],{z24\.h-z27\.h},z14\.h\[5\]' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w11,0:1\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,14:15\],z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],z31\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],z0\.h,z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w10,2:3\],z25\.h,z7\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w11,0:1\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,6:7\],{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z30\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z31\.h,z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z31\.h-z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w9,4:5\],{z19\.h-z20\.h},z13\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w11,0:1\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,6:7\],{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z28\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z29\.h-z0\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z30\.h,z31\.h,z0\.h,z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z30\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z31\.h,z0\.h,z1\.h,z2\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z31\.h-z2\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w9,4:5\],{z25\.h-z28\.h},z14\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1,vgx2\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w11,0:1\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,6:7\],{z0\.h-z1\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z30\.h-z31\.h},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z0\.h-z1\.h},{z30\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w10,2:3\],{z22\.h-z23\.h},{z18\.h-z19\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1,vgx4\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w11,0:1\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,6:7\],{z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z28\.h-z31\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w8,0:1\],{z0\.h-z3\.h},{z28\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `umlsl za\.s\[w11,4:5\],{z16\.h-z19\.h},{z24\.h-z27\.h}' diff --git a/gas/testsuite/gas/aarch64/sme2-12.d b/gas/testsuite/gas/aarch64/sme2-12.d new file mode 100644 index 00000000000..958a1bd3f58 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-12.d @@ -0,0 +1,579 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c1801010 bfmlal za\.s\[w8, 0:1\], z0\.h, z0\.h\[0\] +[^:]+: c1801010 bfmlal za\.s\[w8, 0:1\], z0\.h, z0\.h\[0\] +[^:]+: c1801010 bfmlal za\.s\[w8, 0:1\], z0\.h, z0\.h\[0\] +[^:]+: c1807010 bfmlal za\.s\[w11, 0:1\], z0\.h, z0\.h\[0\] +[^:]+: c1801017 bfmlal za\.s\[w8, 14:15\], z0\.h, z0\.h\[0\] +[^:]+: c18013f0 bfmlal za\.s\[w8, 0:1\], z31\.h, z0\.h\[0\] +[^:]+: c18f1010 bfmlal za\.s\[w8, 0:1\], z0\.h, z15\.h\[0\] +[^:]+: c1809c10 bfmlal za\.s\[w8, 0:1\], z0\.h, z0\.h\[7\] +[^:]+: c1893ab5 bfmlal za\.s\[w9, 10:11\], z21\.h, z9\.h\[2\] +[^:]+: c1901010 bfmlal za\.s\[w8, 0:1, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\] +[^:]+: c1901010 bfmlal za\.s\[w8, 0:1, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\] +[^:]+: c1901010 bfmlal za\.s\[w8, 0:1, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\] +[^:]+: c1901010 bfmlal za\.s\[w8, 0:1, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\] +[^:]+: c1907010 bfmlal za\.s\[w11, 0:1, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\] +[^:]+: c1901013 bfmlal za\.s\[w8, 6:7, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\] +[^:]+: c19013d0 bfmlal za\.s\[w8, 0:1, vgx2\], {z30\.h-z31\.h}, z0\.h\[0\] +[^:]+: c19f1010 bfmlal za\.s\[w8, 0:1, vgx2\], {z0\.h-z1\.h}, z15\.h\[0\] +[^:]+: c1901c14 bfmlal za\.s\[w8, 0:1, vgx2\], {z0\.h-z1\.h}, z0\.h\[7\] +[^:]+: c1993656 bfmlal za\.s\[w9, 4:5, vgx2\], {z18\.h-z19\.h}, z9\.h\[3\] +[^:]+: c1909010 bfmlal za\.s\[w8, 0:1, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\] +[^:]+: c1909010 bfmlal za\.s\[w8, 0:1, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\] +[^:]+: c1909010 bfmlal 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c1e10818 umlsl za\.s\[w8, 0:1, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h} +[^:]+: c1e10818 umlsl za\.s\[w8, 0:1, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h} +[^:]+: c1e16818 umlsl za\.s\[w11, 0:1, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h} +[^:]+: c1e1081b umlsl za\.s\[w8, 6:7, vgx4\], {z0\.h-z3\.h}, {z0\.h-z3\.h} +[^:]+: c1e10b98 umlsl za\.s\[w8, 0:1, vgx4\], {z28\.h-z31\.h}, {z0\.h-z3\.h} +[^:]+: c1fd0818 umlsl za\.s\[w8, 0:1, vgx4\], {z0\.h-z3\.h}, {z28\.h-z31\.h} +[^:]+: c1f96a1a umlsl za\.s\[w11, 4:5, vgx4\], {z16\.h-z19\.h}, {z24\.h-z27\.h} diff --git a/gas/testsuite/gas/aarch64/sme2-12.s b/gas/testsuite/gas/aarch64/sme2-12.s new file mode 100644 index 00000000000..5210e40fe15 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-12.s @@ -0,0 +1,633 @@ + bfmlal za.s[w8, 0:1], z0.h, z0.h[0] + BFMLAL ZA.s[W8, 0:1], Z0.h, Z0.h[0] + BFMLAL ZA.S[W8, 0:1], Z0.H, Z0.H[0] + bfmlal za.s[w11, 0:1], z0.h, z0.h[0] + bfmlal za.s[w8, 14:15], z0.h, z0.h[0] + bfmlal za.s[w8, 0:1], z31.h, z0.h[0] + bfmlal za.s[w8, 0:1], z0.h, z15.h[0] + bfmlal za.s[w8, 0:1], z0.h, z0.h[7] + bfmlal za.s[w9, 10:11], z21.h, z9.h[2] + + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, z0.h[0] + bfmlal za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h[0] + BFMLAL ZA.s[W8, 0:1, VGx2], { Z0.h - Z1.h }, Z0.h[0] + BFMLAL ZA.S[W8, 0:1, VGX2], { Z0.H - Z1.H }, Z0.H[0] + bfmlal za.s[w11, 0:1], { z0.h - z1.h }, z0.h[0] + bfmlal za.s[w8, 6:7], { z0.h - z1.h }, z0.h[0] + bfmlal za.s[w8, 0:1], { z30.h - z31.h }, z0.h[0] + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, z15.h[0] + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, z0.h[7] + bfmlal za.s[w9, 4:5], { z18.h - z19.h }, z9.h[3] + + bfmlal za.s[w8, 0:1], { z0.h - z3.h }, z0.h[0] + bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0] + BFMLAL ZA.s[W8, 0:1, VGx4], { Z0.h - Z3.h }, Z0.h[0] + BFMLAL ZA.S[W8, 0:1, VGX4], { Z0.H - Z3.H }, Z0.H[0] + bfmlal za.s[w11, 0:1], { z0.h - z3.h }, z0.h[0] + bfmlal za.s[w8, 6:7], { z0.h - z3.h }, z0.h[0] + bfmlal za.s[w8, 0:1], { z28.h - z31.h }, z0.h[0] + bfmlal za.s[w8, 0:1], { z0.h - z3.h }, z15.h[0] + bfmlal za.s[w8, 0:1], { z0.h - z3.h }, z0.h[7] + bfmlal za.s[w9, 4:5], { z24.h - z27.h }, z14.h[5] + + bfmlal za.s[w8, 0:1], z0.h, z0.h + BFMLAL ZA.s[W8, 0:1], Z0.h, Z0.h + BFMLAL ZA.S[W8, 0:1], Z0.H, Z0.H + bfmlal za.s[w11, 0:1], z0.h, z0.h + bfmlal za.s[w8, 14:15], z0.h, z0.h + bfmlal za.s[w8, 0:1], z31.h, z0.h + bfmlal za.s[w8, 0:1], z0.h, z15.h + bfmlal za.s[w10, 2:3], z25.h, z7.h + + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, z0.h + bfmlal za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h + BFMLAL ZA.s[W8, 0:1, VGx2], { Z0.h - Z1.h }, Z0.h + BFMLAL ZA.S[W8, 0:1, VGX2], { Z0.H - Z1.H }, Z0.H + bfmlal za.s[w11, 0:1], { z0.h - z1.h }, z0.h + bfmlal za.s[w8, 6:7], { z0.h - z1.h }, z0.h + bfmlal za.s[w8, 0:1], { z1.h - z2.h }, z0.h + bfmlal za.s[w8, 0:1], { z30.h - z31.h }, z0.h + bfmlal za.s[w8, 0:1], { z31.h, z0.h }, z0.h + bfmlal za.s[w8, 0:1], { z31.h - z0.h }, z0.h + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, z15.h + bfmlal za.s[w9, 4:5], { z18.h - z19.h }, z13.h + + bfmlal za.s[w8, 0:1], { z0.h - z3.h }, z0.h + bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h + BFMLAL ZA.s[W8, 0:1, VGx4], { Z0.h - Z3.h }, Z0.h + BFMLAL ZA.S[W8, 0:1, VGX4], { Z0.H - Z3.H }, Z0.H + bfmlal za.s[w11, 0:1], { z0.h - z3.h }, z0.h + bfmlal za.s[w8, 6:7], { z0.h - z3.h }, z0.h + bfmlal za.s[w11, 0:1], { z1.h - z4.h }, z0.h + bfmlal za.s[w8, 0:1], { z28.h - z31.h }, z0.h + bfmlal za.s[w8, 0:1], { z29.h, z30.h, z31.h, z0.h }, z0.h + bfmlal za.s[w8, 0:1], { z29.h - z0.h }, z0.h + bfmlal za.s[w8, 0:1], { z30.h, z31.h, z0.h, z1.h }, z0.h + bfmlal za.s[w8, 0:1], { z30.h - z1.h }, z0.h + bfmlal za.s[w8, 0:1], { z31.h, z0.h, z1.h, z2.h }, z0.h + bfmlal za.s[w8, 0:1], { z31.h - z2.h }, z0.h + bfmlal za.s[w8, 0:1], { z0.h - z3.h }, z15.h + bfmlal za.s[w9, 4:5], { z24.h - z27.h }, z14.h + + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + bfmlal za.s[w8, 0:1, vgx2], { z0.h - z1.h }, { z0.h - z1.h } + BFMLAL ZA.s[W8, 0:1, VGx2], { Z0.h - Z1.h }, { Z0.h - Z1.h } + BFMLAL ZA.S[W8, 0:1, VGX2], { Z0.H - Z1.H }, { Z0.H - Z1.H } + bfmlal za.s[w11, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + bfmlal za.s[w8, 6:7], { z0.h - z1.h }, { z0.h - z1.h } + bfmlal za.s[w8, 0:1], { z30.h - z31.h }, { z0.h - z1.h } + bfmlal za.s[w8, 0:1], { z0.h - z1.h }, { z30.h - z31.h } + bfmlal za.s[w10, 2:3], { z22.h - z23.h }, { z18.h - z19.h } + + bfmlal za.s[w8, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h } + BFMLAL ZA.s[W8, 0:1, VGx4], { Z0.h - Z3.h }, { Z0.h - Z3.h } + BFMLAL ZA.S[W8, 0:1, VGX4], { Z0.H - Z3.H }, { Z0.H - Z3.H } + bfmlal za.s[w11, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + bfmlal za.s[w8, 6:7], { z0.h - z3.h }, { z0.h - z3.h } + bfmlal za.s[w8, 0:1], { z28.h - z31.h }, { z0.h - z3.h } + bfmlal za.s[w8, 0:1], { z0.h - z3.h }, { z28.h - z31.h } + bfmlal za.s[w11, 4:5], { z16.h - z19.h }, { z24.h - z27.h } + + bfmlsl za.s[w8, 0:1], z0.h, z0.h[0] + BFMLSL ZA.s[W8, 0:1], Z0.h, Z0.h[0] + BFMLSL ZA.S[W8, 0:1], Z0.H, Z0.H[0] + bfmlsl za.s[w11, 0:1], z0.h, z0.h[0] + bfmlsl za.s[w8, 14:15], z0.h, z0.h[0] + bfmlsl za.s[w8, 0:1], z31.h, z0.h[0] + bfmlsl za.s[w8, 0:1], z0.h, z15.h[0] + bfmlsl za.s[w8, 0:1], z0.h, z0.h[7] + bfmlsl za.s[w9, 10:11], z21.h, z9.h[2] + + bfmlsl za.s[w8, 0:1], { z0.h - z1.h }, z0.h[0] + bfmlsl za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h[0] + BFMLSL ZA.s[W8, 0:1, VGx2], { Z0.h - Z1.h }, Z0.h[0] + BFMLSL ZA.S[W8, 0:1, VGX2], { Z0.H - Z1.H }, Z0.H[0] + bfmlsl za.s[w11, 0:1], { z0.h - z1.h }, z0.h[0] + bfmlsl za.s[w8, 6:7], { z0.h - z1.h }, z0.h[0] + bfmlsl za.s[w8, 0:1], { z30.h - z31.h }, z0.h[0] + bfmlsl za.s[w8, 0:1], { z0.h - z1.h }, z15.h[0] + bfmlsl za.s[w8, 0:1], { z0.h - z1.h }, z0.h[7] + bfmlsl za.s[w9, 4:5], { z18.h - z19.h }, z9.h[3] + + bfmlsl za.s[w8, 0:1], { z0.h - z3.h }, z0.h[0] + bfmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0] + BFMLSL ZA.s[W8, 0:1, VGx4], { Z0.h - Z3.h }, Z0.h[0] + BFMLSL ZA.S[W8, 0:1, VGX4], { Z0.H - Z3.H }, Z0.H[0] + bfmlsl za.s[w11, 0:1], { z0.h - z3.h }, z0.h[0] + bfmlsl za.s[w8, 6:7], { z0.h - z3.h }, z0.h[0] + bfmlsl za.s[w8, 0:1], { z28.h - z31.h }, z0.h[0] + bfmlsl za.s[w8, 0:1], { z0.h - z3.h }, z15.h[0] + bfmlsl za.s[w8, 0:1], { z0.h - z3.h }, z0.h[7] + bfmlsl za.s[w9, 4:5], { z24.h - z27.h }, z14.h[5] + + bfmlsl za.s[w8, 0:1], z0.h, z0.h + BFMLSL ZA.s[W8, 0:1], Z0.h, Z0.h + BFMLSL ZA.S[W8, 0:1], Z0.H, Z0.H + bfmlsl za.s[w11, 0:1], z0.h, z0.h + bfmlsl za.s[w8, 14:15], z0.h, z0.h + bfmlsl za.s[w8, 0:1], z31.h, z0.h + bfmlsl za.s[w8, 0:1], z0.h, z15.h + bfmlsl za.s[w10, 2:3], z25.h, z7.h + + bfmlsl za.s[w8, 0:1], { z0.h - z1.h }, z0.h + bfmlsl za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h + BFMLSL ZA.s[W8, 0:1, VGx2], { Z0.h - Z1.h }, Z0.h + BFMLSL ZA.S[W8, 0:1, VGX2], { Z0.H - Z1.H }, Z0.H + bfmlsl za.s[w11, 0:1], { z0.h - z1.h }, z0.h + bfmlsl za.s[w8, 6:7], { z0.h - z1.h }, z0.h + bfmlsl za.s[w8, 0:1], { z30.h - z31.h }, z0.h + bfmlsl za.s[w8, 0:1], { z0.h - z1.h }, z15.h + bfmlsl za.s[w9, 4:5], { z18.h - z19.h }, z13.h + + bfmlsl za.s[w8, 0:1], { z0.h - z3.h }, z0.h + bfmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h + BFMLSL ZA.s[W8, 0:1, VGx4], { Z0.h - Z3.h }, Z0.h + BFMLSL ZA.S[W8, 0:1, VGX4], { Z0.H - Z3.H }, Z0.H + bfmlsl za.s[w11, 0:1], { z0.h - z3.h }, z0.h + bfmlsl za.s[w8, 6:7], { z0.h - z3.h }, z0.h + bfmlsl za.s[w8, 0:1], { z28.h - z31.h }, z0.h + bfmlsl za.s[w8, 0:1], { z0.h - z3.h }, z15.h + bfmlsl za.s[w9, 4:5], { z24.h - z27.h }, z14.h + + bfmlsl za.s[w8, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + bfmlsl za.s[w8, 0:1, vgx2], { z0.h - z1.h }, { z0.h - z1.h } + BFMLSL ZA.s[W8, 0:1, VGx2], { Z0.h - Z1.h }, { Z0.h - Z1.h } + BFMLSL ZA.S[W8, 0:1, VGX2], { Z0.H - Z1.H }, { Z0.H - Z1.H } + bfmlsl za.s[w11, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + bfmlsl za.s[w8, 6:7], { z0.h - z1.h }, { z0.h - z1.h } + bfmlsl za.s[w8, 0:1], { z30.h - z31.h }, { z0.h - z1.h } + bfmlsl za.s[w8, 0:1], { z0.h - z1.h }, { z30.h - z31.h } + bfmlsl za.s[w10, 2:3], { z22.h - z23.h }, { z18.h - z19.h } + + bfmlsl za.s[w8, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + bfmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h } + BFMLSL ZA.s[W8, 0:1, VGx4], { Z0.h - Z3.h }, { Z0.h - Z3.h } + BFMLSL ZA.S[W8, 0:1, VGX4], { Z0.H - Z3.H }, { Z0.H - Z3.H } + bfmlsl za.s[w11, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + bfmlsl za.s[w8, 6:7], { z0.h - z3.h }, { z0.h - z3.h } + bfmlsl za.s[w8, 0:1], { z28.h - z31.h }, { z0.h - z3.h } + bfmlsl za.s[w8, 0:1], { z0.h - z3.h }, { z28.h - z31.h } + bfmlsl za.s[w11, 4:5], { z16.h - z19.h }, { z24.h - z27.h } + + fmlal za.s[w8, 0:1], z0.h, z0.h[0] + FMLAL ZA.s[W8, 0:1], Z0.h, Z0.h[0] + FMLAL ZA.S[W8, 0:1], Z0.H, Z0.H[0] + fmlal za.s[w11, 0:1], z0.h, z0.h[0] + fmlal za.s[w8, 14:15], z0.h, z0.h[0] + fmlal za.s[w8, 0:1], z31.h, z0.h[0] + fmlal za.s[w8, 0:1], z0.h, z15.h[0] + fmlal za.s[w8, 0:1], z0.h, z0.h[7] + fmlal za.s[w9, 10:11], z21.h, z9.h[2] + + fmlal za.s[w8, 0:1], { z0.h - z1.h }, z0.h[0] + fmlal za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h[0] + FMLAL ZA.s[W8, 0:1, VGx2], { Z0.h - Z1.h }, Z0.h[0] + FMLAL ZA.S[W8, 0:1, VGX2], { Z0.H - Z1.H }, Z0.H[0] + fmlal za.s[w11, 0:1], { z0.h - z1.h }, z0.h[0] + fmlal za.s[w8, 6:7], { z0.h - z1.h }, z0.h[0] + fmlal za.s[w8, 0:1], { z30.h - z31.h }, z0.h[0] + fmlal za.s[w8, 0:1], { z0.h - z1.h }, z15.h[0] + fmlal za.s[w8, 0:1], { z0.h - z1.h }, z0.h[7] + fmlal za.s[w9, 4:5], { z18.h - z19.h }, z9.h[3] + + fmlal za.s[w8, 0:1], { z0.h - z3.h }, z0.h[0] + fmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0] + FMLAL ZA.s[W8, 0:1, VGx4], { Z0.h - Z3.h }, Z0.h[0] + FMLAL ZA.S[W8, 0:1, VGX4], { Z0.H - Z3.H }, Z0.H[0] + fmlal za.s[w11, 0:1], { z0.h - z3.h }, z0.h[0] + fmlal za.s[w8, 6:7], { z0.h - z3.h }, z0.h[0] + fmlal za.s[w8, 0:1], { z28.h - z31.h }, z0.h[0] + fmlal za.s[w8, 0:1], { z0.h - z3.h }, z15.h[0] + fmlal za.s[w8, 0:1], { z0.h - z3.h }, z0.h[7] + fmlal za.s[w9, 4:5], { z24.h - z27.h }, z14.h[5] + + fmlal za.s[w8, 0:1], z0.h, z0.h + FMLAL ZA.s[W8, 0:1], Z0.h, Z0.h + FMLAL ZA.S[W8, 0:1], Z0.H, Z0.H + fmlal za.s[w11, 0:1], z0.h, z0.h + fmlal za.s[w8, 14:15], z0.h, z0.h + fmlal za.s[w8, 0:1], z31.h, z0.h + fmlal za.s[w8, 0:1], z0.h, z15.h + fmlal za.s[w10, 2:3], z25.h, z7.h + + fmlal za.s[w8, 0:1], { z0.h - z1.h }, z0.h + fmlal za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h + FMLAL ZA.s[W8, 0:1, VGx2], { Z0.h - Z1.h }, Z0.h + FMLAL ZA.S[W8, 0:1, VGX2], { Z0.H - Z1.H }, Z0.H + fmlal za.s[w11, 0:1], { z0.h - z1.h }, z0.h + fmlal za.s[w8, 6:7], { z0.h - z1.h }, z0.h + fmlal za.s[w8, 0:1], { z30.h - z31.h }, z0.h + fmlal za.s[w8, 0:1], { z31.h, z0.h }, z0.h + fmlal za.s[w8, 0:1], { z31.h - z0.h }, z0.h + fmlal za.s[w8, 0:1], { z0.h - z1.h }, z15.h + fmlal za.s[w9, 4:5], { z19.h - z20.h }, z13.h + + fmlal za.s[w8, 0:1], { z0.h - z3.h }, z0.h + fmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h + FMLAL ZA.s[W8, 0:1, VGx4], { Z0.h - Z3.h }, Z0.h + FMLAL ZA.S[W8, 0:1, VGX4], { Z0.H - Z3.H }, Z0.H + fmlal za.s[w11, 0:1], { z0.h - z3.h }, z0.h + fmlal za.s[w8, 6:7], { z0.h - z3.h }, z0.h + fmlal za.s[w8, 0:1], { z28.h - z31.h }, z0.h + fmlal za.s[w8, 0:1], { z29.h - z0.h }, z0.h + fmlal za.s[w8, 0:1], { z30.h, z31.h, z0.h, z1.h }, z0.h + fmlal za.s[w8, 0:1], { z30.h - z1.h }, z0.h + fmlal za.s[w8, 0:1], { z31.h - z2.h }, z0.h + fmlal za.s[w8, 0:1], { z0.h - z3.h }, z15.h + fmlal za.s[w9, 4:5], { z25.h - z28.h }, z14.h + + fmlal za.s[w8, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + fmlal za.s[w8, 0:1, vgx2], { z0.h - z1.h }, { z0.h - z1.h } + FMLAL ZA.s[W8, 0:1, VGx2], { Z0.h - Z1.h }, { Z0.h - Z1.h } + FMLAL ZA.S[W8, 0:1, VGX2], { Z0.H - Z1.H }, { Z0.H - Z1.H } + fmlal za.s[w11, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + fmlal za.s[w8, 6:7], { z0.h - z1.h }, { z0.h - z1.h } + fmlal za.s[w8, 0:1], { z30.h - z31.h }, { z0.h - z1.h } + fmlal za.s[w8, 0:1], { z0.h - z1.h }, { z30.h - z31.h } + fmlal za.s[w10, 2:3], { z22.h - z23.h }, { z18.h - z19.h } + + fmlal za.s[w8, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + fmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h } + FMLAL ZA.s[W8, 0:1, VGx4], { Z0.h - Z3.h }, { Z0.h - Z3.h } + FMLAL ZA.S[W8, 0:1, VGX4], { Z0.H - Z3.H }, { Z0.H - Z3.H } + fmlal za.s[w11, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + fmlal za.s[w8, 6:7], { z0.h - z3.h }, { z0.h - z3.h } + fmlal za.s[w8, 0:1], { z28.h - z31.h }, { z0.h - z3.h } + fmlal za.s[w8, 0:1], { z0.h - z3.h }, { z28.h - z31.h } + fmlal za.s[w11, 4:5], { z16.h - z19.h }, { z24.h - z27.h } + + fmlsl za.s[w8, 0:1], z0.h, z0.h[0] + FMLSL ZA.s[W8, 0:1], Z0.h, Z0.h[0] + FMLSL ZA.S[W8, 0:1], Z0.H, Z0.H[0] + fmlsl za.s[w11, 0:1], z0.h, z0.h[0] + fmlsl za.s[w8, 14:15], z0.h, z0.h[0] + fmlsl za.s[w8, 0:1], z31.h, z0.h[0] + fmlsl za.s[w8, 0:1], z0.h, z15.h[0] + fmlsl za.s[w8, 0:1], z0.h, z0.h[7] + fmlsl za.s[w9, 10:11], z21.h, z9.h[2] + + fmlsl za.s[w8, 0:1], { z0.h - z1.h }, z0.h[0] + fmlsl za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h[0] + FMLSL ZA.s[W8, 0:1, VGx2], { Z0.h - Z1.h }, Z0.h[0] + FMLSL ZA.S[W8, 0:1, VGX2], { Z0.H - Z1.H }, Z0.H[0] + fmlsl za.s[w11, 0:1], { z0.h - z1.h }, z0.h[0] + fmlsl za.s[w8, 6:7], { z0.h - z1.h }, z0.h[0] + fmlsl za.s[w8, 0:1], { z30.h - z31.h }, z0.h[0] + fmlsl za.s[w8, 0:1], { z0.h - z1.h }, z15.h[0] + fmlsl za.s[w8, 0:1], { z0.h - z1.h }, z0.h[7] + fmlsl za.s[w9, 4:5], { z18.h - z19.h }, z9.h[3] + + fmlsl za.s[w8, 0:1], { z0.h - z3.h }, z0.h[0] + fmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0] + FMLSL ZA.s[W8, 0:1, VGx4], { Z0.h - Z3.h }, Z0.h[0] + FMLSL ZA.S[W8, 0:1, VGX4], { Z0.H - Z3.H }, Z0.H[0] + fmlsl za.s[w11, 0:1], { z0.h - z3.h }, z0.h[0] + fmlsl za.s[w8, 6:7], { z0.h - z3.h }, z0.h[0] + fmlsl za.s[w8, 0:1], { z28.h - z31.h }, z0.h[0] + fmlsl za.s[w8, 0:1], { z0.h - z3.h }, z15.h[0] + fmlsl za.s[w8, 0:1], { z0.h - z3.h }, z0.h[7] + fmlsl za.s[w9, 4:5], { z24.h - z27.h }, z14.h[5] + + fmlsl za.s[w8, 0:1], z0.h, z0.h + FMLSL ZA.s[W8, 0:1], Z0.h, Z0.h + FMLSL ZA.S[W8, 0:1], Z0.H, Z0.H + fmlsl za.s[w11, 0:1], z0.h, z0.h + fmlsl za.s[w8, 14:15], z0.h, z0.h + fmlsl za.s[w8, 0:1], z31.h, z0.h + fmlsl za.s[w8, 0:1], z0.h, z15.h + fmlsl za.s[w10, 2:3], z25.h, z7.h + + fmlsl za.s[w8, 0:1], { z0.h - z1.h }, z0.h + fmlsl za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h + FMLSL ZA.s[W8, 0:1, VGx2], { Z0.h - Z1.h }, Z0.h + FMLSL ZA.S[W8, 0:1, VGX2], { Z0.H - Z1.H }, Z0.H + fmlsl za.s[w11, 0:1], { z0.h - z1.h }, z0.h + fmlsl za.s[w8, 6:7], { z0.h - z1.h }, z0.h + fmlsl za.s[w8, 0:1], { z30.h - z31.h }, z0.h + fmlsl za.s[w8, 0:1], { z31.h, z0.h }, z0.h + fmlsl za.s[w8, 0:1], { z31.h - z0.h }, z0.h + fmlsl za.s[w8, 0:1], { z0.h - z1.h }, z15.h + fmlsl za.s[w9, 4:5], { z19.h - z20.h }, z13.h + + fmlsl za.s[w8, 0:1], { z0.h - z3.h }, z0.h + fmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h + FMLSL ZA.s[W8, 0:1, VGx4], { Z0.h - Z3.h }, Z0.h + FMLSL ZA.S[W8, 0:1, VGX4], { Z0.H - Z3.H }, Z0.H + fmlsl za.s[w11, 0:1], { z0.h - z3.h }, z0.h + fmlsl za.s[w8, 6:7], { z0.h - z3.h }, z0.h + fmlsl za.s[w8, 0:1], { z28.h - z31.h }, z0.h + fmlsl za.s[w8, 0:1], { z29.h - z0.h }, z0.h + fmlsl za.s[w8, 0:1], { z30.h, z31.h, z0.h, z1.h }, z0.h + fmlsl za.s[w8, 0:1], { z30.h - z1.h }, z0.h + fmlsl za.s[w8, 0:1], { z31.h - z2.h }, z0.h + fmlsl za.s[w8, 0:1], { z0.h - z3.h }, z15.h + fmlsl za.s[w9, 4:5], { z25.h - z28.h }, z14.h + + fmlsl za.s[w8, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + fmlsl za.s[w8, 0:1, vgx2], { z0.h - z1.h }, { z0.h - z1.h } + FMLSL ZA.s[W8, 0:1, VGx2], { Z0.h - Z1.h }, { Z0.h - Z1.h } + FMLSL ZA.S[W8, 0:1, VGX2], { Z0.H - Z1.H }, { Z0.H - Z1.H } + fmlsl za.s[w11, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + fmlsl za.s[w8, 6:7], { z0.h - z1.h }, { z0.h - z1.h } + fmlsl za.s[w8, 0:1], { z30.h - z31.h }, { z0.h - z1.h } + fmlsl za.s[w8, 0:1], { z0.h - z1.h }, { z30.h - z31.h } + fmlsl za.s[w10, 2:3], { z22.h - z23.h }, { z18.h - z19.h } + + fmlsl za.s[w8, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + fmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h } + FMLSL ZA.s[W8, 0:1, VGx4], { Z0.h - Z3.h }, { Z0.h - Z3.h } + FMLSL ZA.S[W8, 0:1, VGX4], { Z0.H - Z3.H }, { Z0.H - Z3.H } + fmlsl za.s[w11, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + fmlsl za.s[w8, 6:7], { z0.h - z3.h }, { z0.h - z3.h } + fmlsl za.s[w8, 0:1], { z28.h - z31.h }, { z0.h - z3.h } + fmlsl za.s[w8, 0:1], { z0.h - z3.h }, { z28.h - z31.h } + fmlsl za.s[w11, 4:5], { z16.h - z19.h }, { z24.h - z27.h } + + smlal za.s[w8, 0:1], z0.h, z0.h[0] + smlal za.s[w11, 0:1], z0.h, z0.h[0] + smlal za.s[w8, 14:15], z0.h, z0.h[0] + smlal za.s[w8, 0:1], z31.h, z0.h[0] + smlal za.s[w8, 0:1], z0.h, z15.h[0] + smlal za.s[w8, 0:1], z0.h, z0.h[7] + smlal za.s[w9, 10:11], z21.h, z9.h[2] + + smlal za.s[w8, 0:1], { z0.h - z1.h }, z0.h[0] + smlal za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h[0] + smlal za.s[w11, 0:1], { z0.h - z1.h }, z0.h[0] + smlal za.s[w8, 6:7], { z0.h - z1.h }, z0.h[0] + smlal za.s[w8, 0:1], { z30.h - z31.h }, z0.h[0] + smlal za.s[w8, 0:1], { z0.h - z1.h }, z15.h[0] + smlal za.s[w8, 0:1], { z0.h - z1.h }, z0.h[7] + smlal za.s[w9, 4:5], { z18.h - z19.h }, z9.h[3] + + smlal za.s[w8, 0:1], { z0.h - z3.h }, z0.h[0] + smlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0] + smlal za.s[w11, 0:1], { z0.h - z3.h }, z0.h[0] + smlal za.s[w8, 6:7], { z0.h - z3.h }, z0.h[0] + smlal za.s[w8, 0:1], { z28.h - z31.h }, z0.h[0] + smlal za.s[w8, 0:1], { z0.h - z3.h }, z15.h[0] + smlal za.s[w8, 0:1], { z0.h - z3.h }, z0.h[7] + smlal za.s[w9, 4:5], { z24.h - z27.h }, z14.h[5] + + smlal za.s[w8, 0:1], z0.h, z0.h + smlal za.s[w11, 0:1], z0.h, z0.h + smlal za.s[w8, 14:15], z0.h, z0.h + smlal za.s[w8, 0:1], z31.h, z0.h + smlal za.s[w8, 0:1], z0.h, z15.h + smlal za.s[w10, 2:3], z25.h, z7.h + + smlal za.s[w8, 0:1], { z0.h - z1.h }, z0.h + smlal za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h + smlal za.s[w11, 0:1], { z0.h - z1.h }, z0.h + smlal za.s[w8, 6:7], { z0.h - z1.h }, z0.h + smlal za.s[w8, 0:1], { z30.h - z31.h }, z0.h + smlal za.s[w8, 0:1], { z31.h, z0.h }, z0.h + smlal za.s[w8, 0:1], { z31.h - z0.h }, z0.h + smlal za.s[w8, 0:1], { z0.h - z1.h }, z15.h + smlal za.s[w9, 4:5], { z19.h - z20.h }, z13.h + + smlal za.s[w8, 0:1], { z0.h - z3.h }, z0.h + smlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h + smlal za.s[w11, 0:1], { z0.h - z3.h }, z0.h + smlal za.s[w8, 6:7], { z0.h - z3.h }, z0.h + smlal za.s[w8, 0:1], { z28.h - z31.h }, z0.h + smlal za.s[w8, 0:1], { z29.h - z0.h }, z0.h + smlal za.s[w8, 0:1], { z30.h, z31.h, z0.h, z1.h }, z0.h + smlal za.s[w8, 0:1], { z30.h - z1.h }, z0.h + smlal za.s[w8, 0:1], { z31.h, z0.h, z1.h, z2.h }, z0.h + smlal za.s[w8, 0:1], { z31.h - z2.h }, z0.h + smlal za.s[w8, 0:1], { z0.h - z3.h }, z15.h + smlal za.s[w9, 4:5], { z25.h - z28.h }, z14.h + + smlal za.s[w8, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + smlal za.s[w8, 0:1, vgx2], { z0.h - z1.h }, { z0.h - z1.h } + smlal za.s[w11, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + smlal za.s[w8, 6:7], { z0.h - z1.h }, { z0.h - z1.h } + smlal za.s[w8, 0:1], { z30.h - z31.h }, { z0.h - z1.h } + smlal za.s[w8, 0:1], { z0.h - z1.h }, { z30.h - z31.h } + smlal za.s[w10, 2:3], { z22.h - z23.h }, { z18.h - z19.h } + + smlal za.s[w8, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + smlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h } + smlal za.s[w11, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + smlal za.s[w8, 6:7], { z0.h - z3.h }, { z0.h - z3.h } + smlal za.s[w8, 0:1], { z28.h - z31.h }, { z0.h - z3.h } + smlal za.s[w8, 0:1], { z0.h - z3.h }, { z28.h - z31.h } + smlal za.s[w11, 4:5], { z16.h - z19.h }, { z24.h - z27.h } + + smlsl za.s[w8, 0:1], z0.h, z0.h[0] + smlsl za.s[w11, 0:1], z0.h, z0.h[0] + smlsl za.s[w8, 14:15], z0.h, z0.h[0] + smlsl za.s[w8, 0:1], z31.h, z0.h[0] + smlsl za.s[w8, 0:1], z0.h, z15.h[0] + smlsl za.s[w8, 0:1], z0.h, z0.h[7] + smlsl za.s[w9, 10:11], z21.h, z9.h[2] + + smlsl za.s[w8, 0:1], { z0.h - z1.h }, z0.h[0] + smlsl za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h[0] + smlsl za.s[w11, 0:1], { z0.h - z1.h }, z0.h[0] + smlsl za.s[w8, 6:7], { z0.h - z1.h }, z0.h[0] + smlsl za.s[w8, 0:1], { z30.h - z31.h }, z0.h[0] + smlsl za.s[w8, 0:1], { z0.h - z1.h }, z15.h[0] + smlsl za.s[w8, 0:1], { z0.h - z1.h }, z0.h[7] + smlsl za.s[w9, 4:5], { z18.h - z19.h }, z9.h[3] + + smlsl za.s[w8, 0:1], { z0.h - z3.h }, z0.h[0] + smlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0] + smlsl za.s[w11, 0:1], { z0.h - z3.h }, z0.h[0] + smlsl za.s[w8, 6:7], { z0.h - z3.h }, z0.h[0] + smlsl za.s[w8, 0:1], { z28.h - z31.h }, z0.h[0] + smlsl za.s[w8, 0:1], { z0.h - z3.h }, z15.h[0] + smlsl za.s[w8, 0:1], { z0.h - z3.h }, z0.h[7] + smlsl za.s[w9, 4:5], { z24.h - z27.h }, z14.h[5] + + smlsl za.s[w8, 0:1], z0.h, z0.h + smlsl za.s[w11, 0:1], z0.h, z0.h + smlsl za.s[w8, 14:15], z0.h, z0.h + smlsl za.s[w8, 0:1], z31.h, z0.h + smlsl za.s[w8, 0:1], z0.h, z15.h + smlsl za.s[w10, 2:3], z25.h, z7.h + + smlsl za.s[w8, 0:1], { z0.h - z1.h }, z0.h + smlsl za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h + smlsl za.s[w11, 0:1], { z0.h - z1.h }, z0.h + smlsl za.s[w8, 6:7], { z0.h - z1.h }, z0.h + smlsl za.s[w8, 0:1], { z30.h - z31.h }, z0.h + smlsl za.s[w8, 0:1], { z31.h, z0.h }, z0.h + smlsl za.s[w8, 0:1], { z31.h - z0.h }, z0.h + smlsl za.s[w8, 0:1], { z0.h - z1.h }, z15.h + smlsl za.s[w9, 4:5], { z19.h - z20.h }, z13.h + + smlsl za.s[w8, 0:1], { z0.h - z3.h }, z0.h + smlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h + smlsl za.s[w11, 0:1], { z0.h - z3.h }, z0.h + smlsl za.s[w8, 6:7], { z0.h - z3.h }, z0.h + smlsl za.s[w8, 0:1], { z28.h - z31.h }, z0.h + smlsl za.s[w8, 0:1], { z29.h - z0.h }, z0.h + smlsl za.s[w8, 0:1], { z30.h, z31.h, z0.h, z1.h }, z0.h + smlsl za.s[w8, 0:1], { z30.h - z1.h }, z0.h + smlsl za.s[w8, 0:1], { z31.h, z0.h, z1.h, z2.h }, z0.h + smlsl za.s[w8, 0:1], { z31.h - z2.h }, z0.h + smlsl za.s[w8, 0:1], { z0.h - z3.h }, z15.h + smlsl za.s[w9, 4:5], { z25.h - z28.h }, z14.h + + smlsl za.s[w8, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + smlsl za.s[w8, 0:1, vgx2], { z0.h - z1.h }, { z0.h - z1.h } + smlsl za.s[w11, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + smlsl za.s[w8, 6:7], { z0.h - z1.h }, { z0.h - z1.h } + smlsl za.s[w8, 0:1], { z30.h - z31.h }, { z0.h - z1.h } + smlsl za.s[w8, 0:1], { z0.h - z1.h }, { z30.h - z31.h } + smlsl za.s[w10, 2:3], { z22.h - z23.h }, { z18.h - z19.h } + + smlsl za.s[w8, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + smlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h } + smlsl za.s[w11, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + smlsl za.s[w8, 6:7], { z0.h - z3.h }, { z0.h - z3.h } + smlsl za.s[w8, 0:1], { z28.h - z31.h }, { z0.h - z3.h } + smlsl za.s[w8, 0:1], { z0.h - z3.h }, { z28.h - z31.h } + smlsl za.s[w11, 4:5], { z16.h - z19.h }, { z24.h - z27.h } + + umlal za.s[w8, 0:1], z0.h, z0.h[0] + umlal za.s[w11, 0:1], z0.h, z0.h[0] + umlal za.s[w8, 14:15], z0.h, z0.h[0] + umlal za.s[w8, 0:1], z31.h, z0.h[0] + umlal za.s[w8, 0:1], z0.h, z15.h[0] + umlal za.s[w8, 0:1], z0.h, z0.h[7] + umlal za.s[w9, 10:11], z21.h, z9.h[2] + + umlal za.s[w8, 0:1], { z0.h - z1.h }, z0.h[0] + umlal za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h[0] + umlal za.s[w11, 0:1], { z0.h - z1.h }, z0.h[0] + umlal za.s[w8, 6:7], { z0.h - z1.h }, z0.h[0] + umlal za.s[w8, 0:1], { z30.h - z31.h }, z0.h[0] + umlal za.s[w8, 0:1], { z0.h - z1.h }, z15.h[0] + umlal za.s[w8, 0:1], { z0.h - z1.h }, z0.h[7] + umlal za.s[w9, 4:5], { z18.h - z19.h }, z9.h[3] + + umlal za.s[w8, 0:1], { z0.h - z3.h }, z0.h[0] + umlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0] + umlal za.s[w11, 0:1], { z0.h - z3.h }, z0.h[0] + umlal za.s[w8, 6:7], { z0.h - z3.h }, z0.h[0] + umlal za.s[w8, 0:1], { z28.h - z31.h }, z0.h[0] + umlal za.s[w8, 0:1], { z0.h - z3.h }, z15.h[0] + umlal za.s[w8, 0:1], { z0.h - z3.h }, z0.h[7] + umlal za.s[w9, 4:5], { z24.h - z27.h }, z14.h[5] + + umlal za.s[w8, 0:1], z0.h, z0.h + umlal za.s[w11, 0:1], z0.h, z0.h + umlal za.s[w8, 14:15], z0.h, z0.h + umlal za.s[w8, 0:1], z31.h, z0.h + umlal za.s[w8, 0:1], z0.h, z15.h + umlal za.s[w10, 2:3], z25.h, z7.h + + umlal za.s[w8, 0:1], { z0.h - z1.h }, z0.h + umlal za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h + umlal za.s[w11, 0:1], { z0.h - z1.h }, z0.h + umlal za.s[w8, 6:7], { z0.h - z1.h }, z0.h + umlal za.s[w8, 0:1], { z30.h - z31.h }, z0.h + umlal za.s[w8, 0:1], { z31.h, z0.h }, z0.h + umlal za.s[w8, 0:1], { z31.h - z0.h }, z0.h + umlal za.s[w8, 0:1], { z0.h - z1.h }, z15.h + umlal za.s[w9, 4:5], { z19.h - z20.h }, z13.h + + umlal za.s[w8, 0:1], { z0.h - z3.h }, z0.h + umlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h + umlal za.s[w11, 0:1], { z0.h - z3.h }, z0.h + umlal za.s[w8, 6:7], { z0.h - z3.h }, z0.h + umlal za.s[w8, 0:1], { z28.h - z31.h }, z0.h + umlal za.s[w8, 0:1], { z29.h - z0.h }, z0.h + umlal za.s[w8, 0:1], { z30.h, z31.h, z0.h, z1.h }, z0.h + umlal za.s[w8, 0:1], { z30.h - z1.h }, z0.h + umlal za.s[w8, 0:1], { z31.h, z0.h, z1.h, z2.h }, z0.h + umlal za.s[w8, 0:1], { z31.h - z2.h }, z0.h + umlal za.s[w8, 0:1], { z0.h - z3.h }, z15.h + umlal za.s[w9, 4:5], { z25.h - z28.h }, z14.h + + umlal za.s[w8, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + umlal za.s[w8, 0:1, vgx2], { z0.h - z1.h }, { z0.h - z1.h } + umlal za.s[w11, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + umlal za.s[w8, 6:7], { z0.h - z1.h }, { z0.h - z1.h } + umlal za.s[w8, 0:1], { z30.h - z31.h }, { z0.h - z1.h } + umlal za.s[w8, 0:1], { z0.h - z1.h }, { z30.h - z31.h } + umlal za.s[w10, 2:3], { z22.h - z23.h }, { z18.h - z19.h } + + umlal za.s[w8, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + umlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h } + umlal za.s[w11, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + umlal za.s[w8, 6:7], { z0.h - z3.h }, { z0.h - z3.h } + umlal za.s[w8, 0:1], { z28.h - z31.h }, { z0.h - z3.h } + umlal za.s[w8, 0:1], { z0.h - z3.h }, { z28.h - z31.h } + umlal za.s[w11, 4:5], { z16.h - z19.h }, { z24.h - z27.h } + + umlsl za.s[w8, 0:1], z0.h, z0.h[0] + umlsl za.s[w11, 0:1], z0.h, z0.h[0] + umlsl za.s[w8, 14:15], z0.h, z0.h[0] + umlsl za.s[w8, 0:1], z31.h, z0.h[0] + umlsl za.s[w8, 0:1], z0.h, z15.h[0] + umlsl za.s[w8, 0:1], z0.h, z0.h[7] + umlsl za.s[w9, 10:11], z21.h, z9.h[2] + + umlsl za.s[w8, 0:1], { z0.h - z1.h }, z0.h[0] + umlsl za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h[0] + umlsl za.s[w11, 0:1], { z0.h - z1.h }, z0.h[0] + umlsl za.s[w8, 6:7], { z0.h - z1.h }, z0.h[0] + umlsl za.s[w8, 0:1], { z30.h - z31.h }, z0.h[0] + umlsl za.s[w8, 0:1], { z0.h - z1.h }, z15.h[0] + umlsl za.s[w8, 0:1], { z0.h - z1.h }, z0.h[7] + umlsl za.s[w9, 4:5], { z18.h - z19.h }, z9.h[3] + + umlsl za.s[w8, 0:1], { z0.h - z3.h }, z0.h[0] + umlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0] + umlsl za.s[w11, 0:1], { z0.h - z3.h }, z0.h[0] + umlsl za.s[w8, 6:7], { z0.h - z3.h }, z0.h[0] + umlsl za.s[w8, 0:1], { z28.h - z31.h }, z0.h[0] + umlsl za.s[w8, 0:1], { z0.h - z3.h }, z15.h[0] + umlsl za.s[w8, 0:1], { z0.h - z3.h }, z0.h[7] + umlsl za.s[w9, 4:5], { z24.h - z27.h }, z14.h[5] + + umlsl za.s[w8, 0:1], z0.h, z0.h + umlsl za.s[w11, 0:1], z0.h, z0.h + umlsl za.s[w8, 14:15], z0.h, z0.h + umlsl za.s[w8, 0:1], z31.h, z0.h + umlsl za.s[w8, 0:1], z0.h, z15.h + umlsl za.s[w10, 2:3], z25.h, z7.h + + umlsl za.s[w8, 0:1], { z0.h - z1.h }, z0.h + umlsl za.s[w8, 0:1, vgx2], { z0.h - z1.h }, z0.h + umlsl za.s[w11, 0:1], { z0.h - z1.h }, z0.h + umlsl za.s[w8, 6:7], { z0.h - z1.h }, z0.h + umlsl za.s[w8, 0:1], { z30.h - z31.h }, z0.h + umlsl za.s[w8, 0:1], { z31.h, z0.h }, z0.h + umlsl za.s[w8, 0:1], { z31.h - z0.h }, z0.h + umlsl za.s[w8, 0:1], { z0.h - z1.h }, z15.h + umlsl za.s[w9, 4:5], { z19.h - z20.h }, z13.h + + umlsl za.s[w8, 0:1], { z0.h - z3.h }, z0.h + umlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h + umlsl za.s[w11, 0:1], { z0.h - z3.h }, z0.h + umlsl za.s[w8, 6:7], { z0.h - z3.h }, z0.h + umlsl za.s[w8, 0:1], { z28.h - z31.h }, z0.h + umlsl za.s[w8, 0:1], { z29.h - z0.h }, z0.h + umlsl za.s[w8, 0:1], { z30.h, z31.h, z0.h, z1.h }, z0.h + umlsl za.s[w8, 0:1], { z30.h - z1.h }, z0.h + umlsl za.s[w8, 0:1], { z31.h, z0.h, z1.h, z2.h }, z0.h + umlsl za.s[w8, 0:1], { z31.h - z2.h }, z0.h + umlsl za.s[w8, 0:1], { z0.h - z3.h }, z15.h + umlsl za.s[w9, 4:5], { z25.h - z28.h }, z14.h + + umlsl za.s[w8, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + umlsl za.s[w8, 0:1, vgx2], { z0.h - z1.h }, { z0.h - z1.h } + umlsl za.s[w11, 0:1], { z0.h - z1.h }, { z0.h - z1.h } + umlsl za.s[w8, 6:7], { z0.h - z1.h }, { z0.h - z1.h } + umlsl za.s[w8, 0:1], { z30.h - z31.h }, { z0.h - z1.h } + umlsl za.s[w8, 0:1], { z0.h - z1.h }, { z30.h - z31.h } + umlsl za.s[w10, 2:3], { z22.h - z23.h }, { z18.h - z19.h } + + umlsl za.s[w8, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + umlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h } + umlsl za.s[w11, 0:1], { z0.h - z3.h }, { z0.h - z3.h } + umlsl za.s[w8, 6:7], { z0.h - z3.h }, { z0.h - z3.h } + umlsl za.s[w8, 0:1], { z28.h - z31.h }, { z0.h - z3.h } + umlsl za.s[w8, 0:1], { z0.h - z3.h }, { z28.h - z31.h } + umlsl za.s[w11, 4:5], { z16.h - z19.h }, { z24.h - z27.h } diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 8c7646a0ce3..3b58bfaf146 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -510,14 +510,18 @@ enum aarch64_opnd AARCH64_OPND_SME_PNn3_INDEX2, /* Indexed pred-as-counter reg, bits [9:5]. */ AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */ AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */ + AARCH64_OPND_SME_ZA_array_off2x2, /* SME ZA[, #*2:*2+1]. */ AARCH64_OPND_SME_ZA_array_off3_0, /* SME ZA[{, #}]. */ AARCH64_OPND_SME_ZA_array_off3_5, /* SME ZA[{, #}]. */ + AARCH64_OPND_SME_ZA_array_off3x2, /* SME ZA[, #*2:*2+1]. */ AARCH64_OPND_SME_ZA_array_off4, /* SME ZA[{, #}]. */ AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [{, #, MUL VL}]. */ AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ AARCH64_OPND_SME_PnT_Wm_imm, /* SME .[, #]. */ AARCH64_OPND_SME_Zm_INDEX1, /* Zn.T[index], bits [19:16,10]. */ AARCH64_OPND_SME_Zm_INDEX2, /* Zn.T[index], bits [19:16,11:10]. */ + AARCH64_OPND_SME_Zm_INDEX3_2, /* Zn.T[index], bits [19:16,11:10,2]. */ + AARCH64_OPND_SME_Zm_INDEX3_10, /* Zn.T[index], bits [19:16,15,11:10]. */ AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */ AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */ AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */ diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index b4ce19d8194..badf3dc4c2a 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -685,7 +685,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 259: + case 263: return aarch64_ins_reglane (self, info, code, inst, errors); case 36: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -731,12 +731,12 @@ aarch64_insert_operand (const aarch64_operand *self, case 193: case 194: case 237: - case 253: - case 254: - case 256: + case 257: case 258: - case 263: - case 264: + case 260: + case 262: + case 267: + case 268: return aarch64_ins_imm (self, info, code, inst, errors); case 44: case 45: @@ -805,8 +805,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 107: return aarch64_ins_prfop (self, info, code, inst, errors); case 108: - case 255: - case 257: + case 259: + case 261: return aarch64_ins_none (self, info, code, inst, errors); case 109: return aarch64_ins_hint (self, info, code, inst, errors); @@ -919,28 +919,32 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); case 235: case 236: - case 245: - case 246: case 247: case 248: case 249: case 250: case 251: case 252: + case 253: + case 254: + case 255: + case 256: return aarch64_ins_simple_index (self, info, code, inst, errors); case 239: case 240: case 241: - return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 242: - return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 243: - return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 244: + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); + case 245: + return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + case 246: return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); - case 260: - case 261: - case 262: + case 264: + case 265: + case 266: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index f2b7d7d2d62..b1d2d589a13 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1487,8 +1487,10 @@ aarch64_ins_sme_za_array (const aarch64_operand *self, { int regno = info->indexed_za.index.regno & 3; int imm = info->indexed_za.index.imm; + int countm1 = info->indexed_za.index.countm1; + assert (imm % (countm1 + 1) == 0); insert_field (self->fields[0], code, regno, 0); - insert_field (self->fields[1], code, imm, 0); + insert_field (self->fields[1], code, imm / (countm1 + 1), 0); return true; } diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index bfe2bc25e9d..a7578ca0bbc 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -166,7 +166,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x10x100xxxxxxxxxxxxxxxxx zero. */ - return 2670; + return 2734; } } } @@ -190,7 +190,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x101xx0xxxxxxxxxxxxxx luti4. */ - return 2539; + return 2571; } else { @@ -198,7 +198,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x101xx1xxxxxxxxxxxxxx luti4. */ - return 2538; + return 2570; } } else @@ -207,7 +207,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x10x101xxxxxxxxxxxxxxxxx luti4. */ - return 2537; + return 2569; } } } @@ -226,7 +226,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0x010xxxxx00xxxxxxxxxx mov. */ - return 2546; + return 2578; } else { @@ -234,7 +234,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0x011xxxxx00xxxxxxxxxx mov. */ - return 2542; + return 2574; } } else @@ -247,7 +247,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x11xxx0xx00xxxxxxxxxx luti2. */ - return 2536; + return 2568; } else { @@ -255,7 +255,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x11xxx1xx00xxxxxxxxxx luti2. */ - return 2535; + return 2567; } } else @@ -268,7 +268,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010x110xxxxx00xxxxxxxxxx movt. */ - return 2557; + return 2589; } else { @@ -276,7 +276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010x111xxxxx00xxxxxxxxxx movt. */ - return 2556; + return 2588; } } else @@ -285,7 +285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000110x11xxxxxx00xxxxxxxxxx luti2. */ - return 2534; + return 2566; } } } @@ -298,7 +298,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx10xxxxxxxxxx mov. */ - return 2544; + return 2576; } else { @@ -306,7 +306,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx10xxxxxxxxxx mov. */ - return 2540; + return 2572; } } } @@ -320,7 +320,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx01xxxxxxxxxx mov. */ - return 2547; + return 2579; } else { @@ -328,7 +328,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx01xxxxxxxxxx mov. */ - return 2543; + return 2575; } } else @@ -339,7 +339,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx11xxxxxxxxxx mov. */ - return 2545; + return 2577; } else { @@ -347,7 +347,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx11xxxxxxxxxx mov. */ - return 2541; + return 2573; } } } @@ -374,7 +374,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx000xxxxxxxxxxxx0 ld1b. */ - return 2473; + return 2505; } else { @@ -382,7 +382,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx100xxxxxxxxxxxx0 ld1b. */ - return 2474; + return 2506; } } else @@ -393,7 +393,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx010xxxxxxxxxxxx0 ld1w. */ - return 2497; + return 2529; } else { @@ -401,7 +401,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx110xxxxxxxxxxxx0 ld1w. */ - return 2498; + return 2530; } } } @@ -415,7 +415,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx001xxxxxxxxxxxx0 ld1h. */ - return 2489; + return 2521; } else { @@ -423,7 +423,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx101xxxxxxxxxxxx0 ld1h. */ - return 2490; + return 2522; } } else @@ -434,7 +434,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx011xxxxxxxxxxxx0 ld1d. */ - return 2481; + return 2513; } else { @@ -442,7 +442,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx111xxxxxxxxxxxx0 ld1d. */ - return 2482; + return 2514; } } } @@ -459,7 +459,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx000xxxxxxxxxxxx1 ldnt1b. */ - return 2505; + return 2537; } else { @@ -467,7 +467,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx100xxxxxxxxxxxx1 ldnt1b. */ - return 2506; + return 2538; } } else @@ -478,7 +478,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx010xxxxxxxxxxxx1 ldnt1w. */ - return 2529; + return 2561; } else { @@ -486,7 +486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx110xxxxxxxxxxxx1 ldnt1w. */ - return 2530; + return 2562; } } } @@ -500,7 +500,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx001xxxxxxxxxxxx1 ldnt1h. */ - return 2521; + return 2553; } else { @@ -508,7 +508,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx101xxxxxxxxxxxx1 ldnt1h. */ - return 2522; + return 2554; } } else @@ -519,7 +519,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx011xxxxxxxxxxxx1 ldnt1d. */ - return 2513; + return 2545; } else { @@ -527,7 +527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx111xxxxxxxxxxxx1 ldnt1d. */ - return 2514; + return 2546; } } } @@ -591,7 +591,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx000xxxxxxxxxxxx0 ld1b. */ - return 2469; + return 2501; } else { @@ -599,7 +599,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx100xxxxxxxxxxxx0 ld1b. */ - return 2470; + return 2502; } } else @@ -610,7 +610,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx010xxxxxxxxxxxx0 ld1w. */ - return 2493; + return 2525; } else { @@ -618,7 +618,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx110xxxxxxxxxxxx0 ld1w. */ - return 2494; + return 2526; } } } @@ -632,7 +632,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx001xxxxxxxxxxxx0 ld1h. */ - return 2485; + return 2517; } else { @@ -640,7 +640,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx101xxxxxxxxxxxx0 ld1h. */ - return 2486; + return 2518; } } else @@ -651,7 +651,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx011xxxxxxxxxxxx0 ld1d. */ - return 2477; + return 2509; } else { @@ -659,7 +659,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx111xxxxxxxxxxxx0 ld1d. */ - return 2478; + return 2510; } } } @@ -676,7 +676,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx000xxxxxxxxxxxx1 ldnt1b. */ - return 2501; + return 2533; } else { @@ -684,7 +684,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx100xxxxxxxxxxxx1 ldnt1b. */ - return 2502; + return 2534; } } else @@ -695,7 +695,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx010xxxxxxxxxxxx1 ldnt1w. */ - return 2525; + return 2557; } else { @@ -703,7 +703,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx110xxxxxxxxxxxx1 ldnt1w. */ - return 2526; + return 2558; } } } @@ -717,7 +717,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx001xxxxxxxxxxxx1 ldnt1h. */ - return 2517; + return 2549; } else { @@ -725,7 +725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx101xxxxxxxxxxxx1 ldnt1h. */ - return 2518; + return 2550; } } else @@ -736,7 +736,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx011xxxxxxxxxxxx1 ldnt1d. */ - return 2509; + return 2541; } else { @@ -744,7 +744,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx111xxxxxxxxxxxx1 ldnt1d. */ - return 2510; + return 2542; } } } @@ -812,7 +812,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2583; + return 2631; } else { @@ -820,7 +820,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2584; + return 2632; } } else @@ -831,7 +831,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2607; + return 2655; } else { @@ -839,7 +839,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2608; + return 2656; } } } @@ -853,7 +853,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2599; + return 2647; } else { @@ -861,7 +861,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2600; + return 2648; } } else @@ -872,7 +872,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2591; + return 2639; } else { @@ -880,7 +880,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2592; + return 2640; } } } @@ -897,7 +897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2615; + return 2663; } else { @@ -905,7 +905,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2616; + return 2664; } } else @@ -916,7 +916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2639; + return 2687; } else { @@ -924,7 +924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2640; + return 2688; } } } @@ -938,7 +938,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2631; + return 2679; } else { @@ -946,7 +946,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2632; + return 2680; } } else @@ -957,7 +957,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2623; + return 2671; } else { @@ -965,7 +965,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2624; + return 2672; } } } @@ -1029,7 +1029,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2579; + return 2627; } else { @@ -1037,7 +1037,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2580; + return 2628; } } else @@ -1048,7 +1048,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2603; + return 2651; } else { @@ -1056,7 +1056,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2604; + return 2652; } } } @@ -1070,7 +1070,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2595; + return 2643; } else { @@ -1078,7 +1078,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2596; + return 2644; } } else @@ -1089,7 +1089,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2587; + return 2635; } else { @@ -1097,7 +1097,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2588; + return 2636; } } } @@ -1114,7 +1114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2611; + return 2659; } else { @@ -1122,7 +1122,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2612; + return 2660; } } else @@ -1133,7 +1133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2635; + return 2683; } else { @@ -1141,7 +1141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2636; + return 2684; } } } @@ -1155,7 +1155,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2627; + return 2675; } else { @@ -1163,7 +1163,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2628; + return 2676; } } else @@ -1174,7 +1174,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2619; + return 2667; } else { @@ -1182,7 +1182,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2620; + return 2668; } } } @@ -1274,7 +1274,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx000xxxxxxxxx0xxx ld1b. */ - return 2475; + return 2507; } else { @@ -1282,7 +1282,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx010xxxxxxxxx0xxx ld1w. */ - return 2499; + return 2531; } } else @@ -1293,7 +1293,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx001xxxxxxxxx0xxx ld1h. */ - return 2491; + return 2523; } else { @@ -1301,7 +1301,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx011xxxxxxxxx0xxx ld1d. */ - return 2483; + return 2515; } } } @@ -1315,7 +1315,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx000xxxxxxxxx1xxx ldnt1b. */ - return 2507; + return 2539; } else { @@ -1323,7 +1323,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx010xxxxxxxxx1xxx ldnt1w. */ - return 2531; + return 2563; } } else @@ -1334,7 +1334,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx001xxxxxxxxx1xxx ldnt1h. */ - return 2523; + return 2555; } else { @@ -1342,7 +1342,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx011xxxxxxxxx1xxx ldnt1d. */ - return 2515; + return 2547; } } } @@ -1370,7 +1370,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx100xxxxxxxxx0xxx ld1b. */ - return 2476; + return 2508; } else { @@ -1378,7 +1378,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x00001000xxxxx100xxxxxxxxx0xxx ldr. */ - return 2533; + return 2565; } } else @@ -1387,7 +1387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx110xxxxxxxxx0xxx ld1w. */ - return 2500; + return 2532; } } else @@ -1398,7 +1398,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx101xxxxxxxxx0xxx ld1h. */ - return 2492; + return 2524; } else { @@ -1406,7 +1406,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx111xxxxxxxxx0xxx ld1d. */ - return 2484; + return 2516; } } } @@ -1420,7 +1420,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx100xxxxxxxxx1xxx ldnt1b. */ - return 2508; + return 2540; } else { @@ -1428,7 +1428,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx110xxxxxxxxx1xxx ldnt1w. */ - return 2532; + return 2564; } } else @@ -1439,7 +1439,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx101xxxxxxxxx1xxx ldnt1h. */ - return 2524; + return 2556; } else { @@ -1447,7 +1447,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx111xxxxxxxxx1xxx ldnt1d. */ - return 2516; + return 2548; } } } @@ -1455,42 +1455,174 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 4) & 0x1) == 0) + if (((word >> 3) & 0x1) == 0) { - if (((word >> 29) & 0x1) == 0) + if (((word >> 4) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx000001100xxxxxxxxxxxxxxxx0xxxx - bfmopa. */ - return 2363; + if (((word >> 29) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001100xxxxxxxxxxxxxxxx00xxx + bfmopa. */ + return 2363; + } + else + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011000xxxxxxxxxxxxxxx00xxx + fmlal. */ + return 2477; + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011001xxxx0xxxxxxxxxx00xxx + fmlal. */ + return 2478; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011001xxxx1xxxxxxxxxx00xxx + fmlal. */ + return 2479; + } + } + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001100xxxxxxxxxxxxxxxx00xxx + usmopa. */ + return 2384; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx100001100xxxxxxxxxxxxxxxx0xxxx - usmopa. */ - return 2384; + if (((word >> 29) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001100xxxxxxxxxxxxxxxx10xxx + bfmops. */ + return 2364; + } + else + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011000xxxxxxxxxxxxxxx10xxx + bfmlal. */ + return 2436; + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011001xxxx0xxxxxxxxxx10xxx + bfmlal. */ + return 2437; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011001xxxx1xxxxxxxxxx10xxx + bfmlal. */ + return 2438; + } + } + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001100xxxxxxxxxxxxxxxx10xxx + usmops. */ + return 2386; + } } } else { - if (((word >> 29) & 0x1) == 0) + if (((word >> 4) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx000001100xxxxxxxxxxxxxxxx1xxxx - bfmops. */ - return 2364; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000011000xxxxxxxxxxxxxxx01xxx + fmlsl. */ + return 2491; + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000011001xxxx0xxxxxxxxxx01xxx + fmlsl. */ + return 2492; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000011001xxxx1xxxxxxxxxx01xxx + fmlsl. */ + return 2493; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx100001100xxxxxxxxxxxxxxxx1xxxx - usmops. */ - return 2386; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000011000xxxxxxxxxxxxxxx11xxx + bfmlsl. */ + return 2444; + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000011001xxxx0xxxxxxxxxx11xxx + bfmlsl. */ + return 2445; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000011001xxxx1xxxxxxxxxx11xxx + bfmlsl. */ + return 2446; + } + } } } } @@ -1513,7 +1645,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010100xxxx000xxxxxxxxx0xxx ld1b. */ - return 2471; + return 2503; } else { @@ -1521,7 +1653,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010100xxxx010xxxxxxxxx0xxx ld1w. */ - return 2495; + return 2527; } } else @@ -1532,7 +1664,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010100xxxx001xxxxxxxxx0xxx ld1h. */ - return 2487; + return 2519; } else { @@ -1540,7 +1672,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010100xxxx011xxxxxxxxx0xxx ld1d. */ - return 2479; + return 2511; } } } @@ -1552,7 +1684,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xxxxxxxxxx00xxx fmla. */ - return 2455; + return 2471; } else { @@ -1560,7 +1692,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xxxxxxxxxx10xxx fmls. */ - return 2461; + return 2485; } } } @@ -1576,7 +1708,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010100xxxx100xxxxxxxxx0xxx ld1b. */ - return 2472; + return 2504; } else { @@ -1584,7 +1716,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010100xxxx110xxxxxxxxx0xxx ld1w. */ - return 2496; + return 2528; } } else @@ -1595,7 +1727,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010100xxxx101xxxxxxxxx0xxx ld1h. */ - return 2488; + return 2520; } else { @@ -1603,7 +1735,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010100xxxx111xxxxxxxxx0xxx ld1d. */ - return 2480; + return 2512; } } } @@ -1615,7 +1747,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xxxxxxxxxx00xxx fmla. */ - return 2456; + return 2472; } else { @@ -1623,7 +1755,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xxxxxxxxxx10xxx fmls. */ - return 2462; + return 2486; } } } @@ -1640,7 +1772,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx000xxxxxxxxx1xxx ldnt1b. */ - return 2503; + return 2535; } else { @@ -1648,7 +1780,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx100xxxxxxxxx1xxx ldnt1b. */ - return 2504; + return 2536; } } else @@ -1659,7 +1791,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx010xxxxxxxxx1xxx ldnt1w. */ - return 2527; + return 2559; } else { @@ -1667,7 +1799,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx110xxxxxxxxx1xxx ldnt1w. */ - return 2528; + return 2560; } } } @@ -1681,7 +1813,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx001xxxxxxxxx1xxx ldnt1h. */ - return 2519; + return 2551; } else { @@ -1689,7 +1821,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx101xxxxxxxxx1xxx ldnt1h. */ - return 2520; + return 2552; } } else @@ -1700,7 +1832,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx011xxxxxxxxx1xxx ldnt1d. */ - return 2511; + return 2543; } else { @@ -1708,7 +1840,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx111xxxxxxxxx1xxx ldnt1d. */ - return 2512; + return 2544; } } } @@ -1720,23 +1852,89 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 29) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + if (((word >> 3) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx000001110xxxxx0xxxxxxxxxx0xxxx - fmla. */ - return 2671; + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001110xxxxx0xx0xxxxxxx00xxx + fmla. */ + return 2735; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001110xxxxx1xx0xxxxxxx00xxx + fmla. */ + return 2736; + } + } + else + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011100xxxxxxx1xxxxxxx00xxx + smlal. */ + return 2603; + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx0xx1xxxxxxx00xxx + smlal. */ + return 2604; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx1xx1xxxxxxx00xxx + smlal. */ + return 2605; + } + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx000001110xxxxx1xxxxxxxxxx0xxxx - fmla. */ - return 2672; - } - } + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011100xxxxxxxxxxxxxxx01xxx + smlsl. */ + return 2611; + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx0xxxxxxxxxx01xxx + smlsl. */ + return 2612; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx1xxxxxxxxxx01xxx + smlsl. */ + return 2613; + } + } + } + } else { if (((word >> 30) & 0x1) == 0) @@ -1759,32 +1957,98 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 29) & 0x1) == 0) + if (((word >> 3) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + if (((word >> 29) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx000001110xxxxx0xxxxxxxxxx1xxxx - fmls. */ - return 2673; + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001110xxxxx0xx0xxxxxxx10xxx + fmls. */ + return 2737; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001110xxxxx1xx0xxxxxxx10xxx + fmls. */ + return 2738; + } + } + else + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011100xxxxxxx1xxxxxxx10xxx + umlal. */ + return 2706; + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx0xx1xxxxxxx10xxx + umlal. */ + return 2707; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0000011101xxxx1xx1xxxxxxx10xxx + umlal. */ + return 2708; + } + } + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xx000001110xxxxx1xxxxxxxxxx1xxxx - fmls. */ - return 2674; + xx100001110xxxxxxxxxxxxxxxx10xxx + usmops. */ + return 2387; } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx100001110xxxxxxxxxxxxxxxx1xxxx - usmops. */ - return 2387; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000011100xxxxxxxxxxxxxxx11xxx + umlsl. */ + return 2714; + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000011101xxxx0xxxxxxxxxx11xxx + umlsl. */ + return 2715; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000011101xxxx1xxxxxxxxxx11xxx + umlsl. */ + return 2716; + } + } } } } @@ -1823,23 +2087,152 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 10) & 0x1) == 0) { - if (((word >> 23) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010010xxxx0xx0x0xxxxx00xxx + fmlal. */ + return 2481; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010011xxxx0xx0x0xxxxx00xxx + fmlal. */ + return 2482; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001101xxxx00xx0x0xxxxx00xxx + fmlal. */ + return 2483; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001101xxxx10xx0x0xxxxx00xxx + fmlal. */ + return 2484; + } + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010110xxxx0xx0x0xxxxx00xxx + smlal. */ + return 2607; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010111xxxx0xx0x0xxxxx00xxx + smlal. */ + return 2608; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001111xxxx00xx0x0xxxxx00xxx + smlal. */ + return 2609; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001111xxxx10xx0x0xxxxx00xxx + smlal. */ + return 2610; + } + } + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x10xxxx0xx1x0xxxxx00xxx + fmla. */ + return 2473; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x11xxxx0xx1x0xxxxx00xxx + fmla. */ + return 2474; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xx1x0xxxxx00xxx + fmla. */ + return 2475; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xx1x0xxxxx00xxx + fmla. */ + return 2476; + } + } + } + } + else + { + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000010x10xxxx0xxxx0xxxxx00xxx - fmla. */ - return 2457; + x1000001x01xxxxx0xx0x1xxxxx00xxx + fmlal. */ + return 2480; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000010x11xxxx0xxxx0xxxxx00xxx - fmla. */ - return 2458; + x1000001x11xxxxx0xx0x1xxxxx00xxx + smlal. */ + return 2606; } } else @@ -1848,61 +2241,171 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011x1xxxx00xxxx0xxxxx00xxx - fmla. */ - return 2459; + x1000001xx1xxxx00xx1x1xxxxx00xxx + fadd. */ + return 2453; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011x1xxxx10xxxx0xxxxx00xxx - fmla. */ - return 2460; + x1000001xx1xxxx10xx1x1xxxxx00xxx + fadd. */ + return 2454; } } } - else + } + else + { + if (((word >> 10) & 0x1) == 0) { - if (((word >> 16) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx00xxxx1xxxxx00xxx - fadd. */ - return 2437; + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010010xxxx0xx0x0xxxxx10xxx + bfmlal. */ + return 2440; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010011xxxx0xx0x0xxxxx10xxx + bfmlal. */ + return 2441; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001101xxxx00xx0x0xxxxx10xxx + bfmlal. */ + return 2442; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001101xxxx10xx0x0xxxxx10xxx + bfmlal. */ + return 2443; + } + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010110xxxx0xx0x0xxxxx10xxx + umlal. */ + return 2710; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010111xxxx0xx0x0xxxxx10xxx + umlal. */ + return 2711; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001111xxxx00xx0x0xxxxx10xxx + umlal. */ + return 2712; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001111xxxx10xx0x0xxxxx10xxx + umlal. */ + return 2713; + } + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx10xxxx1xxxxx00xxx - fadd. */ - return 2438; + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x10xxxx0xx1x0xxxxx10xxx + add. */ + return 2430; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x11xxxx0xx1x0xxxxx10xxx + add. */ + return 2431; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xx1x0xxxxx10xxx + add. */ + return 2432; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xx1x0xxxxx10xxx + add. */ + return 2433; + } + } } } - } - else - { - if (((word >> 10) & 0x1) == 0) + else { - if (((word >> 23) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000010x10xxxx0xxxx0xxxxx10xxx - add. */ - return 2430; + x1000001x01xxxxx0xx0x1xxxxx10xxx + bfmlal. */ + return 2439; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000010x11xxxx0xxxx0xxxxx10xxx - add. */ - return 2431; + x1000001x11xxxxx0xx0x1xxxxx10xxx + umlal. */ + return 2709; } } else @@ -1911,127 +2414,347 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011x1xxxx00xxxx0xxxxx10xxx + x1000001xx1xxxx00xx1x1xxxxx10xxx add. */ - return 2432; + return 2428; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011x1xxxx10xxxx0xxxxx10xxx + x1000001xx1xxxx10xx1x1xxxxx10xxx add. */ - return 2433; + return 2429; + } + } + } + } + } + else + { + if (((word >> 4) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010010xxxx0xx0x0xxxxx01xxx + fmlsl. */ + return 2495; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010011xxxx0xx0x0xxxxx01xxx + fmlsl. */ + return 2496; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001101xxxx00xx0x0xxxxx01xxx + fmlsl. */ + return 2497; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001101xxxx10xx0x0xxxxx01xxx + fmlsl. */ + return 2498; + } + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010110xxxx0xx0x0xxxxx01xxx + smlsl. */ + return 2615; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010111xxxx0xx0x0xxxxx01xxx + smlsl. */ + return 2616; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001111xxxx00xx0x0xxxxx01xxx + smlsl. */ + return 2617; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001111xxxx10xx0x0xxxxx01xxx + smlsl. */ + return 2618; + } + } + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x10xxxx0xx1x0xxxxx01xxx + fmls. */ + return 2487; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x11xxxx0xx1x0xxxxx01xxx + fmls. */ + return 2488; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xx1x0xxxxx01xxx + fmls. */ + return 2489; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xx1x0xxxxx01xxx + fmls. */ + return 2490; + } } } } else { - if (((word >> 16) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx00xxxx1xxxxx10xxx - add. */ - return 2428; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x01xxxxx0xx0x1xxxxx01xxx + fmlsl. */ + return 2494; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x11xxxxx0xx0x1xxxxx01xxx + smlsl. */ + return 2614; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx10xxxx1xxxxx10xxx - add. */ - return 2429; + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx00xx1x1xxxxx01xxx + fsub. */ + return 2499; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx10xx1x1xxxxx01xxx + fsub. */ + return 2500; + } } } } - } - else - { - if (((word >> 4) & 0x1) == 0) + else { if (((word >> 10) & 0x1) == 0) { - if (((word >> 23) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000010x10xxxx0xxxx0xxxxx01xxx - fmls. */ - return 2463; + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010010xxxx0xx0x0xxxxx11xxx + bfmlsl. */ + return 2448; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010011xxxx0xx0x0xxxxx11xxx + bfmlsl. */ + return 2449; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001101xxxx00xx0x0xxxxx11xxx + bfmlsl. */ + return 2450; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001101xxxx10xx0x0xxxxx11xxx + bfmlsl. */ + return 2451; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000010x11xxxx0xxxx0xxxxx01xxx - fmls. */ - return 2464; + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010110xxxx0xx0x0xxxxx11xxx + umlsl. */ + return 2718; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010111xxxx0xx0x0xxxxx11xxx + umlsl. */ + return 2719; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001111xxxx00xx0x0xxxxx11xxx + umlsl. */ + return 2720; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001111xxxx10xx0x0xxxxx11xxx + umlsl. */ + return 2721; + } + } } } else { - if (((word >> 16) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000011x1xxxx00xxxx0xxxxx01xxx - fmls. */ - return 2465; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x10xxxx0xx1x0xxxxx11xxx + sub. */ + return 2694; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x11xxxx0xx1x0xxxxx11xxx + sub. */ + return 2695; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10000011x1xxxx10xxxx0xxxxx01xxx - fmls. */ - return 2466; + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xx1x0xxxxx11xxx + sub. */ + return 2696; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xx1x0xxxxx11xxx + sub. */ + return 2697; + } } } } else { - if (((word >> 16) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx00xxxx1xxxxx01xxx - fsub. */ - return 2467; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx10xxxx1xxxxx01xxx - fsub. */ - return 2468; - } - } - } - else - { - if (((word >> 10) & 0x1) == 0) - { - if (((word >> 23) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000010x10xxxx0xxxx0xxxxx11xxx - sub. */ - return 2646; + x1000001x01xxxxx0xx0x1xxxxx11xxx + bfmlsl. */ + return 2447; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000010x11xxxx0xxxx0xxxxx11xxx - sub. */ - return 2647; + x1000001x11xxxxx0xx0x1xxxxx11xxx + umlsl. */ + return 2717; } } else @@ -2040,39 +2763,20 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011x1xxxx00xxxx0xxxxx11xxx + x1000001xx1xxxx00xx1x1xxxxx11xxx sub. */ - return 2648; + return 2692; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10000011x1xxxx10xxxx0xxxxx11xxx + x1000001xx1xxxx10xx1x1xxxxx11xxx sub. */ - return 2649; + return 2693; } } } - else - { - if (((word >> 16) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx00xxxx1xxxxx11xxx - sub. */ - return 2644; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx10xxxx1xxxxx11xxx - sub. */ - return 2645; - } - } } } } @@ -2090,7 +2794,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxx01x0xxxxxxx0xxxx0 sel. */ - return 2561; + return 2593; } else { @@ -2098,7 +2802,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxx11x0xxxxxxx0xxxx0 sel. */ - return 2562; + return 2594; } } else @@ -2115,7 +2819,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1000x0xx0xxxx0 smax. */ - return 2563; + return 2595; } else { @@ -2123,7 +2827,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1100x0xx0xxxx0 smax. */ - return 2565; + return 2597; } } else @@ -2134,7 +2838,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1010x0xx0xxxx0 smax. */ - return 2564; + return 2596; } else { @@ -2142,7 +2846,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1110x0xx0xxxx0 smax. */ - return 2566; + return 2598; } } } @@ -2156,7 +2860,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1001x0xx0xxxx0 sqdmulh. */ - return 2571; + return 2619; } else { @@ -2164,7 +2868,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1101x0xx0xxxx0 sqdmulh. */ - return 2573; + return 2621; } } else @@ -2175,7 +2879,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1011x0xx0xxxx0 sqdmulh. */ - return 2572; + return 2620; } else { @@ -2183,7 +2887,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1111x0xx0xxxx0 sqdmulh. */ - return 2574; + return 2622; } } } @@ -2200,7 +2904,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x100x01xx0xxxx0 fmax. */ - return 2439; + return 2455; } else { @@ -2208,7 +2912,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x110x01xx0xxxx0 fmax. */ - return 2441; + return 2457; } } else @@ -2219,7 +2923,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x101x01xx0xxxx0 fmax. */ - return 2440; + return 2456; } else { @@ -2227,7 +2931,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x111x01xx0xxxx0 fmax. */ - return 2442; + return 2458; } } } @@ -2267,7 +2971,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx00x00xx1xxxx0 smin. */ - return 2567; + return 2599; } else { @@ -2275,7 +2979,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx10x00xx1xxxx0 smin. */ - return 2569; + return 2601; } } else @@ -2286,7 +2990,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx01x00xx1xxxx0 smin. */ - return 2568; + return 2600; } else { @@ -2294,7 +2998,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx11x00xx1xxxx0 smin. */ - return 2570; + return 2602; } } } @@ -2308,7 +3012,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx00x10xx1xxxx0 srshl. */ - return 2575; + return 2623; } else { @@ -2316,7 +3020,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx10x10xx1xxxx0 srshl. */ - return 2577; + return 2625; } } else @@ -2327,7 +3031,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx01x10xx1xxxx0 srshl. */ - return 2576; + return 2624; } else { @@ -2335,7 +3039,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx11x10xx1xxxx0 srshl. */ - return 2578; + return 2626; } } } @@ -2350,7 +3054,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx00xx1xx1xxxx0 fmaxnm. */ - return 2443; + return 2459; } else { @@ -2358,7 +3062,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx10xx1xx1xxxx0 fmaxnm. */ - return 2445; + return 2461; } } else @@ -2369,7 +3073,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx01xx1xx1xxxx0 fmaxnm. */ - return 2444; + return 2460; } else { @@ -2377,7 +3081,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx11xx1xx1xxxx0 fmaxnm. */ - return 2446; + return 2462; } } } @@ -2397,7 +3101,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx00xx0xx0xxxx1 umax. */ - return 2650; + return 2698; } else { @@ -2405,7 +3109,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx10xx0xx0xxxx1 umax. */ - return 2652; + return 2700; } } else @@ -2416,7 +3120,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx01xx0xx0xxxx1 umax. */ - return 2651; + return 2699; } else { @@ -2424,7 +3128,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx11xx0xx0xxxx1 umax. */ - return 2653; + return 2701; } } } @@ -2438,7 +3142,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx00xx1xx0xxxx1 fmin. */ - return 2447; + return 2463; } else { @@ -2446,7 +3150,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx10xx1xx0xxxx1 fmin. */ - return 2449; + return 2465; } } else @@ -2457,7 +3161,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx01xx1xx0xxxx1 fmin. */ - return 2448; + return 2464; } else { @@ -2465,7 +3169,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx11xx1xx0xxxx1 fmin. */ - return 2450; + return 2466; } } } @@ -2484,7 +3188,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx00x00xx1xxxx1 umin. */ - return 2654; + return 2702; } else { @@ -2492,7 +3196,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx10x00xx1xxxx1 umin. */ - return 2656; + return 2704; } } else @@ -2503,7 +3207,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx01x00xx1xxxx1 umin. */ - return 2655; + return 2703; } else { @@ -2511,7 +3215,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx11x00xx1xxxx1 umin. */ - return 2657; + return 2705; } } } @@ -2525,7 +3229,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx00x10xx1xxxx1 urshl. */ - return 2658; + return 2722; } else { @@ -2533,7 +3237,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx10x10xx1xxxx1 urshl. */ - return 2660; + return 2724; } } else @@ -2544,7 +3248,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx01x10xx1xxxx1 urshl. */ - return 2659; + return 2723; } else { @@ -2552,7 +3256,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx11x10xx1xxxx1 urshl. */ - return 2661; + return 2725; } } } @@ -2567,7 +3271,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx00xx1xx1xxxx1 fminnm. */ - return 2451; + return 2467; } else { @@ -2575,7 +3279,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx10xx1xx1xxxx1 fminnm. */ - return 2453; + return 2469; } } else @@ -2586,7 +3290,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx01xx1xx1xxxx1 fminnm. */ - return 2452; + return 2468; } else { @@ -2594,7 +3298,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx11xx1xx1xxxx1 fminnm. */ - return 2454; + return 2470; } } } @@ -2623,7 +3327,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx0xxx st1b. */ - return 2585; + return 2633; } else { @@ -2631,7 +3335,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx0xxx st1w. */ - return 2609; + return 2657; } } else @@ -2642,7 +3346,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx0xxx st1h. */ - return 2601; + return 2649; } else { @@ -2650,7 +3354,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx0xxx st1d. */ - return 2593; + return 2641; } } } @@ -2664,7 +3368,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2617; + return 2665; } else { @@ -2672,7 +3376,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2641; + return 2689; } } else @@ -2683,7 +3387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2633; + return 2681; } else { @@ -2691,7 +3395,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2625; + return 2673; } } } @@ -2719,7 +3423,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx100xxxxxxxxx0xxx st1b. */ - return 2586; + return 2634; } else { @@ -2727,7 +3431,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1100001001xxxxx100xxxxxxxxx0xxx str. */ - return 2643; + return 2691; } } else @@ -2736,7 +3440,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx0xxx st1w. */ - return 2610; + return 2658; } } else @@ -2747,7 +3451,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx0xxx st1h. */ - return 2602; + return 2650; } else { @@ -2755,7 +3459,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx0xxx st1d. */ - return 2594; + return 2642; } } } @@ -2769,7 +3473,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2618; + return 2666; } else { @@ -2777,7 +3481,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2642; + return 2690; } } else @@ -2788,7 +3492,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2634; + return 2682; } else { @@ -2796,7 +3500,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2626; + return 2674; } } } @@ -2838,7 +3542,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx0xxx st1b. */ - return 2581; + return 2629; } else { @@ -2846,7 +3550,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx0xxx st1b. */ - return 2582; + return 2630; } } else @@ -2857,7 +3561,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx0xxx st1w. */ - return 2605; + return 2653; } else { @@ -2865,7 +3569,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx0xxx st1w. */ - return 2606; + return 2654; } } } @@ -2879,7 +3583,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx0xxx st1h. */ - return 2597; + return 2645; } else { @@ -2887,7 +3591,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx0xxx st1h. */ - return 2598; + return 2646; } } else @@ -2898,7 +3602,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx0xxx st1d. */ - return 2589; + return 2637; } else { @@ -2906,7 +3610,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx0xxx st1d. */ - return 2590; + return 2638; } } } @@ -2923,7 +3627,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2613; + return 2661; } else { @@ -2931,7 +3635,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2614; + return 2662; } } else @@ -2942,7 +3646,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2637; + return 2685; } else { @@ -2950,7 +3654,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2638; + return 2686; } } } @@ -2964,7 +3668,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2629; + return 2677; } else { @@ -2972,7 +3676,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2630; + return 2678; } } else @@ -2983,7 +3687,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2621; + return 2669; } else { @@ -2991,7 +3695,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2622; + return 2670; } } } @@ -5393,7 +6097,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001000xxxxxxxxx00xxxxxxxxxx stlurb. */ - return 2715; + return 2779; } else { @@ -5401,7 +6105,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2723; + return 2787; } } else @@ -5412,7 +6116,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001000xxxxxxxxx00xxxxxxxxxx stlurh. */ - return 2719; + return 2783; } else { @@ -5420,7 +6124,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2726; + return 2790; } } } @@ -5458,7 +6162,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0000x1xxxxxxxxxx cpyfp. */ - return 2775; + return 2839; } else { @@ -5466,7 +6170,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1000x1xxxxxxxxxx cpyfprn. */ - return 2781; + return 2845; } } else @@ -5477,7 +6181,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0100x1xxxxxxxxxx cpyfpwn. */ - return 2778; + return 2842; } else { @@ -5485,7 +6189,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1100x1xxxxxxxxxx cpyfpn. */ - return 2784; + return 2848; } } } @@ -5499,7 +6203,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0010x1xxxxxxxxxx cpyfprt. */ - return 2799; + return 2863; } else { @@ -5507,7 +6211,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1010x1xxxxxxxxxx cpyfprtrn. */ - return 2805; + return 2869; } } else @@ -5518,7 +6222,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0110x1xxxxxxxxxx cpyfprtwn. */ - return 2802; + return 2866; } else { @@ -5526,7 +6230,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1110x1xxxxxxxxxx cpyfprtn. */ - return 2808; + return 2872; } } } @@ -5543,7 +6247,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0001x1xxxxxxxxxx cpyfpwt. */ - return 2787; + return 2851; } else { @@ -5551,7 +6255,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1001x1xxxxxxxxxx cpyfpwtrn. */ - return 2793; + return 2857; } } else @@ -5562,7 +6266,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0101x1xxxxxxxxxx cpyfpwtwn. */ - return 2790; + return 2854; } else { @@ -5570,7 +6274,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1101x1xxxxxxxxxx cpyfpwtn. */ - return 2796; + return 2860; } } } @@ -5584,7 +6288,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0011x1xxxxxxxxxx cpyfpt. */ - return 2811; + return 2875; } else { @@ -5592,7 +6296,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1011x1xxxxxxxxxx cpyfptrn. */ - return 2817; + return 2881; } } else @@ -5603,7 +6307,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0111x1xxxxxxxxxx cpyfptwn. */ - return 2814; + return 2878; } else { @@ -5611,7 +6315,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1111x1xxxxxxxxxx cpyfptn. */ - return 2820; + return 2884; } } } @@ -5676,7 +6380,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001010xxxxxxxxx00xxxxxxxxxx ldapurb. */ - return 2716; + return 2780; } else { @@ -5684,7 +6388,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2724; + return 2788; } } else @@ -5695,7 +6399,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001010xxxxxxxxx00xxxxxxxxxx ldapurh. */ - return 2720; + return 2784; } else { @@ -5703,7 +6407,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2727; + return 2791; } } } @@ -5741,7 +6445,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0000x1xxxxxxxxxx cpyfm. */ - return 2776; + return 2840; } else { @@ -5749,7 +6453,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1000x1xxxxxxxxxx cpyfmrn. */ - return 2782; + return 2846; } } else @@ -5760,7 +6464,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0100x1xxxxxxxxxx cpyfmwn. */ - return 2779; + return 2843; } else { @@ -5768,7 +6472,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1100x1xxxxxxxxxx cpyfmn. */ - return 2785; + return 2849; } } } @@ -5782,7 +6486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0010x1xxxxxxxxxx cpyfmrt. */ - return 2800; + return 2864; } else { @@ -5790,7 +6494,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1010x1xxxxxxxxxx cpyfmrtrn. */ - return 2806; + return 2870; } } else @@ -5801,7 +6505,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0110x1xxxxxxxxxx cpyfmrtwn. */ - return 2803; + return 2867; } else { @@ -5809,7 +6513,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1110x1xxxxxxxxxx cpyfmrtn. */ - return 2809; + return 2873; } } } @@ -5826,7 +6530,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0001x1xxxxxxxxxx cpyfmwt. */ - return 2788; + return 2852; } else { @@ -5834,7 +6538,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1001x1xxxxxxxxxx cpyfmwtrn. */ - return 2794; + return 2858; } } else @@ -5845,7 +6549,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0101x1xxxxxxxxxx cpyfmwtwn. */ - return 2791; + return 2855; } else { @@ -5853,7 +6557,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1101x1xxxxxxxxxx cpyfmwtn. */ - return 2797; + return 2861; } } } @@ -5867,7 +6571,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0011x1xxxxxxxxxx cpyfmt. */ - return 2812; + return 2876; } else { @@ -5875,7 +6579,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1011x1xxxxxxxxxx cpyfmtrn. */ - return 2818; + return 2882; } } else @@ -5886,7 +6590,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0111x1xxxxxxxxxx cpyfmtwn. */ - return 2815; + return 2879; } else { @@ -5894,7 +6598,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1111x1xxxxxxxxxx cpyfmtn. */ - return 2821; + return 2885; } } } @@ -5962,7 +6666,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001100xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2718; + return 2782; } else { @@ -5970,7 +6674,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001100xxxxxxxxx00xxxxxxxxxx ldapursw. */ - return 2725; + return 2789; } } else @@ -5979,7 +6683,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001100xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2722; + return 2786; } } else @@ -5990,7 +6694,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0011001110xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2717; + return 2781; } else { @@ -5998,7 +6702,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001110xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2721; + return 2785; } } } @@ -6060,7 +6764,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0000x1xxxxxxxxxx cpyfe. */ - return 2777; + return 2841; } else { @@ -6068,7 +6772,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0000x1xxxxxxxxxx setp. */ - return 2871; + return 2935; } } else @@ -6079,7 +6783,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1000x1xxxxxxxxxx cpyfern. */ - return 2783; + return 2847; } else { @@ -6087,7 +6791,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1000x1xxxxxxxxxx sete. */ - return 2873; + return 2937; } } } @@ -6101,7 +6805,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0100x1xxxxxxxxxx cpyfewn. */ - return 2780; + return 2844; } else { @@ -6109,7 +6813,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0100x1xxxxxxxxxx setm. */ - return 2872; + return 2936; } } else @@ -6118,7 +6822,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1100x1xxxxxxxxxx cpyfen. */ - return 2786; + return 2850; } } } @@ -6134,7 +6838,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0010x1xxxxxxxxxx cpyfert. */ - return 2801; + return 2865; } else { @@ -6142,7 +6846,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0010x1xxxxxxxxxx setpn. */ - return 2877; + return 2941; } } else @@ -6153,7 +6857,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1010x1xxxxxxxxxx cpyfertrn. */ - return 2807; + return 2871; } else { @@ -6161,7 +6865,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1010x1xxxxxxxxxx seten. */ - return 2879; + return 2943; } } } @@ -6175,7 +6879,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0110x1xxxxxxxxxx cpyfertwn. */ - return 2804; + return 2868; } else { @@ -6183,7 +6887,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0110x1xxxxxxxxxx setmn. */ - return 2878; + return 2942; } } else @@ -6192,7 +6896,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1110x1xxxxxxxxxx cpyfertn. */ - return 2810; + return 2874; } } } @@ -6211,7 +6915,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0001x1xxxxxxxxxx cpyfewt. */ - return 2789; + return 2853; } else { @@ -6219,7 +6923,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0001x1xxxxxxxxxx setpt. */ - return 2874; + return 2938; } } else @@ -6230,7 +6934,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1001x1xxxxxxxxxx cpyfewtrn. */ - return 2795; + return 2859; } else { @@ -6238,7 +6942,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1001x1xxxxxxxxxx setet. */ - return 2876; + return 2940; } } } @@ -6252,7 +6956,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0101x1xxxxxxxxxx cpyfewtwn. */ - return 2792; + return 2856; } else { @@ -6260,7 +6964,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0101x1xxxxxxxxxx setmt. */ - return 2875; + return 2939; } } else @@ -6269,7 +6973,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1101x1xxxxxxxxxx cpyfewtn. */ - return 2798; + return 2862; } } } @@ -6285,7 +6989,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0011x1xxxxxxxxxx cpyfet. */ - return 2813; + return 2877; } else { @@ -6293,7 +6997,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0011x1xxxxxxxxxx setptn. */ - return 2880; + return 2944; } } else @@ -6304,7 +7008,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1011x1xxxxxxxxxx cpyfetrn. */ - return 2819; + return 2883; } else { @@ -6312,7 +7016,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1011x1xxxxxxxxxx setetn. */ - return 2882; + return 2946; } } } @@ -6326,7 +7030,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0111x1xxxxxxxxxx cpyfetwn. */ - return 2816; + return 2880; } else { @@ -6334,7 +7038,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0111x1xxxxxxxxxx setmtn. */ - return 2881; + return 2945; } } else @@ -6343,7 +7047,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1111x1xxxxxxxxxx cpyfetn. */ - return 2822; + return 2886; } } } @@ -6716,7 +7420,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010110xxxx0x01000xxxxxxxxxx abs. */ - return 2900; + return 2964; } else { @@ -6734,7 +7438,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11000xxxxxxxxxx smax. */ - return 2903; + return 2967; } } } @@ -6814,7 +7518,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx0xx10xxxxxxxxxx setf8. */ - return 2713; + return 2777; } else { @@ -6822,7 +7526,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx1xx10xxxxxxxxxx setf16. */ - return 2714; + return 2778; } } else @@ -6929,7 +7633,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11010xxxxxxxxxx smin. */ - return 2905; + return 2969; } } } @@ -6945,7 +7649,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxx0x00110xxxxxxxxxx ctz. */ - return 2902; + return 2966; } else { @@ -6990,7 +7694,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010000xxxxxxxxx01xxxxxxxxxx rmif. */ - return 2712; + return 2776; } else { @@ -7084,7 +7788,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x10xxxxxx11001xxxxxxxxxx umax. */ - return 2904; + return 2968; } } } @@ -7214,7 +7918,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxxxx11011xxxxxxxxxx umin. */ - return 2906; + return 2970; } } } @@ -7230,7 +7934,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxx0x00111xxxxxxxxxx cnt. */ - return 2901; + return 2965; } else { @@ -8072,7 +8776,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000110xxxxxxxxxx usdot. */ - return 2732; + return 2796; } } } @@ -8146,7 +8850,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000111xxxxxxxxxx sudot. */ - return 2733; + return 2797; } } } @@ -10820,7 +11524,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx011110xxxxxxxxxx usdot. */ - return 2731; + return 2795; } } } @@ -12524,7 +13228,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0100xxx10101xxxxxxxxxxxxx bfcvtnt. */ - return 2760; + return 2824; } } else @@ -12767,7 +13471,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxxx00xxxxxxxxxxxxx ld1rob. */ - return 2736; + return 2800; } else { @@ -12775,7 +13479,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxxx00xxxxxxxxxxxxx ld1roh. */ - return 2737; + return 2801; } } else @@ -13007,7 +13711,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xxxxxxxxxxxxx bfdot. */ - return 2757; + return 2821; } else { @@ -13028,7 +13732,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx0xxxxxxxxxx bfmlalb. */ - return 2764; + return 2828; } else { @@ -13036,7 +13740,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx1xxxxxxxxxx bfmlalt. */ - return 2763; + return 2827; } } else @@ -13091,7 +13795,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx1x0xxxxxxxxxxxxx bfdot. */ - return 2756; + return 2820; } else { @@ -13103,7 +13807,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx0xxxxxxxxxx bfmlalb. */ - return 2762; + return 2826; } else { @@ -13111,7 +13815,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx1xxxxxxxxxx bfmlalt. */ - return 2761; + return 2825; } } else @@ -13162,7 +13866,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxx001xxxxxxxxxxxxx ld1rob. */ - return 2740; + return 2804; } else { @@ -13170,7 +13874,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxx001xxxxxxxxxxxxx ld1roh. */ - return 2741; + return 2805; } } else @@ -13529,7 +14233,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2734; + return 2798; } else { @@ -13562,7 +14266,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx111xxxxxxxxxxxxx bfmmla. */ - return 2758; + return 2822; } else { @@ -13592,7 +14296,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2735; + return 2799; } else { @@ -13721,7 +14425,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x00xxxxxxxxxx zip1. */ - return 2744; + return 2808; } else { @@ -13731,7 +14435,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000010xxxxxxxxxx uzp1. */ - return 2746; + return 2810; } else { @@ -13739,7 +14443,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000110xxxxxxxxxx trn1. */ - return 2748; + return 2812; } } } @@ -13751,7 +14455,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x01xxxxxxxxxx zip2. */ - return 2745; + return 2809; } else { @@ -13761,7 +14465,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000011xxxxxxxxxx uzp2. */ - return 2747; + return 2811; } else { @@ -13769,7 +14473,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000111xxxxxxxxxx trn2. */ - return 2749; + return 2813; } } } @@ -14828,7 +15532,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1000xxxxx100110xxxxxxxxxx smmla. */ - return 2728; + return 2792; } else { @@ -14836,7 +15540,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1100xxxxx100110xxxxxxxxxx usmmla. */ - return 2730; + return 2794; } } else @@ -14845,7 +15549,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1x10xxxxx100110xxxxxxxxxx ummla. */ - return 2729; + return 2793; } } } @@ -16341,7 +17045,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx000xxxxxxxxxxxxx ld1row. */ - return 2738; + return 2802; } else { @@ -16349,7 +17053,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx000xxxxxxxxxxxxx ld1rod. */ - return 2739; + return 2803; } } } @@ -16723,7 +17427,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx001xxxxxxxxxxxxx ld1row. */ - return 2742; + return 2806; } else { @@ -16731,7 +17435,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx001xxxxxxxxxxxxx ld1rod. */ - return 2743; + return 2807; } } } @@ -17092,7 +17796,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx10xxx whilege. */ - return 2662; + return 2726; } else { @@ -17100,7 +17804,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx11xxx whilegt. */ - return 2663; + return 2727; } } else @@ -17130,7 +17834,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011100xxxxx1xxxx pext. */ - return 2558; + return 2590; } } } @@ -17144,7 +17848,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx10xxx whilehs. */ - return 2665; + return 2729; } else { @@ -17152,7 +17856,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx11xxx whilehi. */ - return 2664; + return 2728; } } else @@ -17182,7 +17886,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011110xxxxx1xxxx ptrue. */ - return 2560; + return 2592; } } } @@ -17199,7 +17903,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx10xxx whilelt. */ - return 2669; + return 2733; } else { @@ -17207,7 +17911,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx11xxx whilele. */ - return 2666; + return 2730; } } else @@ -17237,7 +17941,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011101xxxxx1xxxx pext. */ - return 2559; + return 2591; } } } @@ -17251,7 +17955,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx10xxx whilelo. */ - return 2667; + return 2731; } else { @@ -17259,7 +17963,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx11xxx whilels. */ - return 2668; + return 2732; } } else @@ -18385,7 +19089,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x110001x10101xxxxxxxxxxxxx bfcvt. */ - return 2759; + return 2823; } } else @@ -19044,7 +19748,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx10xxxx10xxxx1xxxxxxxxx cntp. */ - return 2436; + return 2452; } } else @@ -19746,7 +20450,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1010100xxxxxxxxxxxxxxxxxxx1xxxx bc.c. */ - return 2895; + return 2959; } else { @@ -20326,7 +21030,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0000xxxxxxxxxxxx cpyp. */ - return 2823; + return 2887; } else { @@ -20334,7 +21038,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0000xxxxxxxxxxxx cpye. */ - return 2825; + return 2889; } } else @@ -20345,7 +21049,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1000xxxxxxxxxxxx cpyprn. */ - return 2829; + return 2893; } else { @@ -20353,7 +21057,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1000xxxxxxxxxxxx cpyern. */ - return 2831; + return 2895; } } } @@ -20367,7 +21071,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0100xxxxxxxxxxxx cpypwn. */ - return 2826; + return 2890; } else { @@ -20375,7 +21079,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0100xxxxxxxxxxxx cpyewn. */ - return 2828; + return 2892; } } else @@ -20386,7 +21090,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1100xxxxxxxxxxxx cpypn. */ - return 2832; + return 2896; } else { @@ -20394,7 +21098,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1100xxxxxxxxxxxx cpyen. */ - return 2834; + return 2898; } } } @@ -20411,7 +21115,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0010xxxxxxxxxxxx cpyprt. */ - return 2847; + return 2911; } else { @@ -20419,7 +21123,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0010xxxxxxxxxxxx cpyert. */ - return 2849; + return 2913; } } else @@ -20430,7 +21134,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1010xxxxxxxxxxxx cpyprtrn. */ - return 2853; + return 2917; } else { @@ -20438,7 +21142,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1010xxxxxxxxxxxx cpyertrn. */ - return 2855; + return 2919; } } } @@ -20452,7 +21156,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0110xxxxxxxxxxxx cpyprtwn. */ - return 2850; + return 2914; } else { @@ -20460,7 +21164,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0110xxxxxxxxxxxx cpyertwn. */ - return 2852; + return 2916; } } else @@ -20471,7 +21175,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1110xxxxxxxxxxxx cpyprtn. */ - return 2856; + return 2920; } else { @@ -20479,7 +21183,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1110xxxxxxxxxxxx cpyertn. */ - return 2858; + return 2922; } } } @@ -20499,7 +21203,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0001xxxxxxxxxxxx cpypwt. */ - return 2835; + return 2899; } else { @@ -20507,7 +21211,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0001xxxxxxxxxxxx cpyewt. */ - return 2837; + return 2901; } } else @@ -20518,7 +21222,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1001xxxxxxxxxxxx cpypwtrn. */ - return 2841; + return 2905; } else { @@ -20526,7 +21230,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1001xxxxxxxxxxxx cpyewtrn. */ - return 2843; + return 2907; } } } @@ -20540,7 +21244,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0101xxxxxxxxxxxx cpypwtwn. */ - return 2838; + return 2902; } else { @@ -20548,7 +21252,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0101xxxxxxxxxxxx cpyewtwn. */ - return 2840; + return 2904; } } else @@ -20559,7 +21263,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1101xxxxxxxxxxxx cpypwtn. */ - return 2844; + return 2908; } else { @@ -20567,7 +21271,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1101xxxxxxxxxxxx cpyewtn. */ - return 2846; + return 2910; } } } @@ -20584,7 +21288,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0011xxxxxxxxxxxx cpypt. */ - return 2859; + return 2923; } else { @@ -20592,7 +21296,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0011xxxxxxxxxxxx cpyet. */ - return 2861; + return 2925; } } else @@ -20603,7 +21307,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1011xxxxxxxxxxxx cpyptrn. */ - return 2865; + return 2929; } else { @@ -20611,7 +21315,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1011xxxxxxxxxxxx cpyetrn. */ - return 2867; + return 2931; } } } @@ -20625,7 +21329,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0111xxxxxxxxxxxx cpyptwn. */ - return 2862; + return 2926; } else { @@ -20633,7 +21337,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0111xxxxxxxxxxxx cpyetwn. */ - return 2864; + return 2928; } } else @@ -20644,7 +21348,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1111xxxxxxxxxxxx cpyptn. */ - return 2868; + return 2932; } else { @@ -20652,7 +21356,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1111xxxxxxxxxxxx cpyetn. */ - return 2870; + return 2934; } } } @@ -20686,7 +21390,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0000xxxxxxxxxxxx cpym. */ - return 2824; + return 2888; } else { @@ -20694,7 +21398,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0000xxxxxxxxxxxx setgp. */ - return 2883; + return 2947; } } else @@ -20705,7 +21409,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1000xxxxxxxxxxxx cpymrn. */ - return 2830; + return 2894; } else { @@ -20713,7 +21417,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1000xxxxxxxxxxxx setge. */ - return 2885; + return 2949; } } } @@ -20727,7 +21431,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0100xxxxxxxxxxxx cpymwn. */ - return 2827; + return 2891; } else { @@ -20735,7 +21439,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0100xxxxxxxxxxxx setgm. */ - return 2884; + return 2948; } } else @@ -20744,7 +21448,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1100xxxxxxxxxxxx cpymn. */ - return 2833; + return 2897; } } } @@ -20760,7 +21464,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0010xxxxxxxxxxxx cpymrt. */ - return 2848; + return 2912; } else { @@ -20768,7 +21472,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0010xxxxxxxxxxxx setgpn. */ - return 2889; + return 2953; } } else @@ -20779,7 +21483,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1010xxxxxxxxxxxx cpymrtrn. */ - return 2854; + return 2918; } else { @@ -20787,7 +21491,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1010xxxxxxxxxxxx setgen. */ - return 2891; + return 2955; } } } @@ -20801,7 +21505,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0110xxxxxxxxxxxx cpymrtwn. */ - return 2851; + return 2915; } else { @@ -20809,7 +21513,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0110xxxxxxxxxxxx setgmn. */ - return 2890; + return 2954; } } else @@ -20818,7 +21522,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1110xxxxxxxxxxxx cpymrtn. */ - return 2857; + return 2921; } } } @@ -20837,7 +21541,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0001xxxxxxxxxxxx cpymwt. */ - return 2836; + return 2900; } else { @@ -20845,7 +21549,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0001xxxxxxxxxxxx setgpt. */ - return 2886; + return 2950; } } else @@ -20856,7 +21560,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1001xxxxxxxxxxxx cpymwtrn. */ - return 2842; + return 2906; } else { @@ -20864,7 +21568,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1001xxxxxxxxxxxx setget. */ - return 2888; + return 2952; } } } @@ -20878,7 +21582,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0101xxxxxxxxxxxx cpymwtwn. */ - return 2839; + return 2903; } else { @@ -20886,7 +21590,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0101xxxxxxxxxxxx setgmt. */ - return 2887; + return 2951; } } else @@ -20895,7 +21599,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1101xxxxxxxxxxxx cpymwtn. */ - return 2845; + return 2909; } } } @@ -20911,7 +21615,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0011xxxxxxxxxxxx cpymt. */ - return 2860; + return 2924; } else { @@ -20919,7 +21623,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0011xxxxxxxxxxxx setgptn. */ - return 2892; + return 2956; } } else @@ -20930,7 +21634,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1011xxxxxxxxxxxx cpymtrn. */ - return 2866; + return 2930; } else { @@ -20938,7 +21642,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1011xxxxxxxxxxxx setgetn. */ - return 2894; + return 2958; } } } @@ -20952,7 +21656,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0111xxxxxxxxxxxx cpymtwn. */ - return 2863; + return 2927; } else { @@ -20960,7 +21664,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0111xxxxxxxxxxxx setgmtn. */ - return 2893; + return 2957; } } else @@ -20969,7 +21673,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1111xxxxxxxxxxxx cpymtn. */ - return 2869; + return 2933; } } } @@ -21136,7 +21840,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1001xxxxxxxxxx smmla. */ - return 2750; + return 2814; } } } @@ -21169,7 +21873,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0101xxxxxxxxxx sdot. */ - return 2676; + return 2740; } } else @@ -21243,7 +21947,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1011xxxxxxxxxx usmmla. */ - return 2752; + return 2816; } } } @@ -21276,7 +21980,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0111xxxxxxxxxx usdot. */ - return 2753; + return 2817; } } else @@ -21323,7 +22027,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110000xxxxxxxxxxxxxxxxxxxxx eor3. */ - return 2683; + return 2747; } else { @@ -21331,7 +22035,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110100xxxxxxxxxxxxxxxxxxxxx xar. */ - return 2685; + return 2749; } } else @@ -21342,7 +22046,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx0xxxxxxxxxxxxxxx sm3ss1. */ - return 2687; + return 2751; } else { @@ -21356,7 +22060,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx00xxxxxxxxxx sm3tt1a. */ - return 2688; + return 2752; } else { @@ -21364,7 +22068,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx00xxxxxxxxxx sha512su0. */ - return 2681; + return 2745; } } else @@ -21373,7 +22077,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx10xxxxxxxxxx sm3tt2a. */ - return 2690; + return 2754; } } else @@ -21386,7 +22090,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx01xxxxxxxxxx sm3tt1b. */ - return 2689; + return 2753; } else { @@ -21394,7 +22098,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx01xxxxxxxxxx sm4e. */ - return 2694; + return 2758; } } else @@ -21403,7 +22107,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx11xxxxxxxxxx sm3tt2b. */ - return 2691; + return 2755; } } } @@ -21584,7 +22288,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx100101xxxxxxxxxx udot. */ - return 2675; + return 2739; } } else @@ -21615,7 +22319,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx101x01xxxxxxxxxx ummla. */ - return 2751; + return 2815; } else { @@ -21634,7 +22338,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx1x1011xxxxxxxxxx bfmmla. */ - return 2767; + return 2831; } else { @@ -21644,7 +22348,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011100x0xxxxx1x1111xxxxxxxxxx bfdot. */ - return 2765; + return 2829; } else { @@ -21654,7 +22358,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x0xxxxx1x1111xxxxxxxxxx bfmlalb. */ - return 2772; + return 2836; } else { @@ -21662,7 +22366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x0xxxxx1x1111xxxxxxxxxx bfmlalt. */ - return 2771; + return 2835; } } } @@ -22246,7 +22950,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000011101x1xxxx1011010xxxxxxxxxx bfcvtn. */ - return 2768; + return 2832; } else { @@ -22254,7 +22958,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010011101x1xxxx1011010xxxxxxxxxx bfcvtn2. */ - return 2769; + return 2833; } } } @@ -22572,7 +23276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx0xxxxxxxxxxxxxxx bcax. */ - return 2686; + return 2750; } } else @@ -23183,7 +23887,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx100000xxxxxxxxxx sha512h. */ - return 2679; + return 2743; } } } @@ -23235,7 +23939,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx110000xxxxxxxxxx sm3partw1. */ - return 2692; + return 2756; } } } @@ -23478,7 +24182,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100010xxxxxxxxxx sha512su1. */ - return 2682; + return 2746; } } else @@ -23554,7 +24258,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110010xxxxxxxxxx sm4ekey. */ - return 2695; + return 2759; } } else @@ -24380,7 +25084,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100001xxxxxxxxxx sha512h2. */ - return 2680; + return 2744; } } else @@ -24412,7 +25116,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110001xxxxxxxxxx sm3partw2. */ - return 2693; + return 2757; } } else @@ -24652,7 +25356,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100011xxxxxxxxxx rax1. */ - return 2684; + return 2748; } } else @@ -24684,7 +25388,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2698; + return 2762; } else { @@ -24692,7 +25396,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2702; + return 2766; } } } @@ -24714,7 +25418,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2699; + return 2763; } else { @@ -24722,7 +25426,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2703; + return 2767; } } } @@ -24761,7 +25465,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2696; + return 2760; } else { @@ -24769,7 +25473,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2700; + return 2764; } } else @@ -24791,7 +25495,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2697; + return 2761; } else { @@ -24799,7 +25503,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2701; + return 2765; } } else @@ -26607,7 +27311,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2704; + return 2768; } else { @@ -26615,7 +27319,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2708; + return 2772; } } else @@ -26637,7 +27341,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2705; + return 2769; } else { @@ -26645,7 +27349,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2709; + return 2773; } } else @@ -27151,7 +27855,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2706; + return 2770; } else { @@ -27159,7 +27863,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2710; + return 2774; } } } @@ -27181,7 +27885,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2707; + return 2771; } else { @@ -27189,7 +27893,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2711; + return 2775; } } } @@ -27245,7 +27949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx001111xxxxxxxx1110x0xxxxxxxxxx sdot. */ - return 2678; + return 2742; } else { @@ -27253,7 +27957,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101111xxxxxxxx1110x0xxxxxxxxxx udot. */ - return 2677; + return 2741; } } } @@ -27356,7 +28060,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx1111x0xxxxxxxxxx sudot. */ - return 2755; + return 2819; } else { @@ -27364,7 +28068,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111110xxxxxx1111x0xxxxxxxxxx usdot. */ - return 2754; + return 2818; } } else @@ -27375,7 +28079,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx1111x0xxxxxxxxxx bfdot. */ - return 2766; + return 2830; } else { @@ -27385,7 +28089,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx1111x0xxxxxxxxxx bfmlalb. */ - return 2774; + return 2838; } else { @@ -27393,7 +28097,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx1111x0xxxxxxxxxx bfmlalt. */ - return 2773; + return 2837; } } } @@ -27884,22 +28588,22 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2391: return NULL; /* mova --> NULL. */ case 2388: value = 2390; break; /* mov --> mova. */ case 2390: return NULL; /* mova --> NULL. */ - case 2546: value = 2554; break; /* mov --> mova. */ - case 2554: return NULL; /* mova --> NULL. */ - case 2542: value = 2550; break; /* mov --> mova. */ - case 2550: return NULL; /* mova --> NULL. */ - case 2544: value = 2552; break; /* mov --> mova. */ - case 2552: return NULL; /* mova --> NULL. */ - case 2540: value = 2548; break; /* mov --> mova. */ - case 2548: return NULL; /* mova --> NULL. */ - case 2547: value = 2555; break; /* mov --> mova. */ - case 2555: return NULL; /* mova --> NULL. */ - case 2543: value = 2551; break; /* mov --> mova. */ - case 2551: return NULL; /* mova --> NULL. */ - case 2545: value = 2553; break; /* mov --> mova. */ - case 2553: return NULL; /* mova --> NULL. */ - case 2541: value = 2549; break; /* mov --> mova. */ - case 2549: return NULL; /* mova --> NULL. */ + case 2578: value = 2586; break; /* mov --> mova. */ + case 2586: return NULL; /* mova --> NULL. */ + case 2574: value = 2582; break; /* mov --> mova. */ + case 2582: return NULL; /* mova --> NULL. */ + case 2576: value = 2584; break; /* mov --> mova. */ + case 2584: return NULL; /* mova --> NULL. */ + case 2572: value = 2580; break; /* mov --> mova. */ + case 2580: return NULL; /* mova --> NULL. */ + case 2579: value = 2587; break; /* mov --> mova. */ + case 2587: return NULL; /* mova --> NULL. */ + case 2575: value = 2583; break; /* mov --> mova. */ + case 2583: return NULL; /* mova --> NULL. */ + case 2577: value = 2585; break; /* mov --> mova. */ + case 2585: return NULL; /* mova --> NULL. */ + case 2573: value = 2581; break; /* mov --> mova. */ + case 2581: return NULL; /* mova --> NULL. */ case 2393: value = 2398; break; /* ld1b --> ld1b. */ case 2398: return NULL; /* ld1b --> NULL. */ case 2395: value = 2400; break; /* ld1w --> ld1w. */ @@ -27921,11 +28625,11 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2407: value = 2412; break; /* st1q --> st1q. */ case 2412: return NULL; /* st1q --> NULL. */ case 12: value = 19; break; /* add --> addg. */ - case 19: value = 2896; break; /* addg --> smax. */ - case 2896: value = 2897; break; /* smax --> umax. */ - case 2897: value = 2898; break; /* umax --> smin. */ - case 2898: value = 2899; break; /* smin --> umin. */ - case 2899: return NULL; /* umin --> NULL. */ + case 19: value = 2960; break; /* addg --> smax. */ + case 2960: value = 2961; break; /* smax --> umax. */ + case 2961: value = 2962; break; /* umax --> smin. */ + case 2962: value = 2963; break; /* smin --> umin. */ + case 2963: return NULL; /* umin --> NULL. */ case 16: value = 20; break; /* sub --> subg. */ case 20: return NULL; /* subg --> NULL. */ case 971: value = 975; break; /* stnp --> stp. */ @@ -28083,8 +28787,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 824: return NULL; /* fsqrt --> NULL. */ case 832: value = 833; break; /* frintz --> frintz. */ case 833: return NULL; /* frintz --> NULL. */ - case 825: value = 2770; break; /* fcvt --> bfcvt. */ - case 2770: return NULL; /* bfcvt --> NULL. */ + case 825: value = 2834; break; /* fcvt --> bfcvt. */ + case 2834: return NULL; /* bfcvt --> NULL. */ case 834: value = 835; break; /* frinta --> frinta. */ case 835: return NULL; /* frinta --> NULL. */ case 836: value = 837; break; /* frintx --> frintx. */ @@ -28613,7 +29317,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 259: + case 263: return aarch64_ext_reglane (self, info, code, inst, errors); case 36: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -28660,12 +29364,12 @@ aarch64_extract_operand (const aarch64_operand *self, case 193: case 194: case 237: - case 253: - case 254: - case 256: + case 257: case 258: - case 263: - case 264: + case 260: + case 262: + case 267: + case 268: return aarch64_ext_imm (self, info, code, inst, errors); case 44: case 45: @@ -28736,8 +29440,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 107: return aarch64_ext_prfop (self, info, code, inst, errors); case 108: - case 255: - case 257: + case 259: + case 261: return aarch64_ext_none (self, info, code, inst, errors); case 109: return aarch64_ext_hint (self, info, code, inst, errors); @@ -28850,28 +29554,32 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); case 235: case 236: - case 245: - case 246: case 247: case 248: case 249: case 250: case 251: case 252: + case 253: + case 254: + case 255: + case 256: return aarch64_ext_simple_index (self, info, code, inst, errors); case 239: case 240: case 241: - return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 242: - return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 243: - return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 244: + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); + case 245: + return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + case 246: return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); - case 260: - case 261: - case 262: + case 264: + case 265: + case 266: return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index bfeab066f0a..7271231eb3f 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -1905,7 +1905,7 @@ aarch64_ext_sme_za_list (const aarch64_operand *self, bool aarch64_ext_sme_za_array (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED, + const aarch64_inst *inst, aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int regno = extract_field (self->fields[0], code, 0); @@ -1914,8 +1914,12 @@ aarch64_ext_sme_za_array (const aarch64_operand *self, else regno += 8; int imm = extract_field (self->fields[1], code, 0); + int num_offsets = get_operand_specific_data (self); + if (num_offsets == 0) + num_offsets = 1; info->indexed_za.index.regno = regno; - info->indexed_za.index.imm = imm; + info->indexed_za.index.imm = imm * num_offsets; + info->indexed_za.index.countm1 = num_offsets - 1; info->indexed_za.group_size = get_opcode_dependent_value (inst->opcode); return true; } diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 51415ceb033..cb209c55a89 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -263,14 +263,18 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX2", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_PNn3, FLD_imm2_8}, "an indexed SVE predicate-as-counter register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off2x2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm2_0}, "ZA array"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_0}, "ZA array"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_5}, "ZA array"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3x2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_0}, "ZA array"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_0}, "ZA array"}, {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10, FLD_imm1_2}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_15, FLD_imm2_10}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm1_16}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_15}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_16}, "an indexed SVE vector register"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index cd37f8ac910..9555df186a4 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -319,9 +319,12 @@ const aarch64_field fields[] = { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */ { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */ { 21, 2 }, /* hw: in move wide constant instructions. */ + { 2, 1 }, /* imm1_2: general immediate in bits [2]. */ { 8, 1 }, /* imm1_8: general immediate in bits [8]. */ { 10, 1 }, /* imm1_10: general immediate in bits [10]. */ + { 15, 1 }, /* imm1_15: general immediate in bits [15]. */ { 16, 1 }, /* imm1_16: general immediate in bits [16]. */ + { 0, 2 }, /* imm2_0: general immediate in bits [1:0]. */ { 8, 2 }, /* imm2_8: general immediate in bits [9:8]. */ { 10, 2 }, /* imm2_10: 2-bit immediate, bits [11:10] */ { 15, 2 }, /* imm2_15: 2-bit immediate, bits [16:15] */ @@ -1769,6 +1772,8 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SME_Zm_INDEX1: case AARCH64_OPND_SME_Zm_INDEX2: + case AARCH64_OPND_SME_Zm_INDEX3_2: + case AARCH64_OPND_SME_Zm_INDEX3_10: size = get_operand_fields_width (get_operand_from_code (type)) - 4; if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 15, 0, (1 << size) - 1)) @@ -1872,6 +1877,18 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, return 0; break; + case AARCH64_OPND_SME_ZA_array_off2x2: + if (!check_za_access (opnd, mismatch_detail, idx, 8, 3, 2, + get_opcode_dependent_value (opcode))) + return 0; + break; + + case AARCH64_OPND_SME_ZA_array_off3x2: + if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 2, + get_opcode_dependent_value (opcode))) + return 0; + break; + case AARCH64_OPND_SME_ZA_HV_idx_srcxN: case AARCH64_OPND_SME_ZA_HV_idx_destxN: size = aarch64_get_qualifier_esize (opnd->qualifier); @@ -3938,6 +3955,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zn_INDEX: case AARCH64_OPND_SME_Zm_INDEX1: case AARCH64_OPND_SME_Zm_INDEX2: + case AARCH64_OPND_SME_Zm_INDEX3_2: + case AARCH64_OPND_SME_Zm_INDEX3_10: case AARCH64_OPND_SME_Zn_INDEX1_16: case AARCH64_OPND_SME_Zn_INDEX2_15: case AARCH64_OPND_SME_Zn_INDEX2_16: @@ -3990,8 +4009,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, print_sme_za_list (buf, size, opnd->reg.regno, styler); break; + case AARCH64_OPND_SME_ZA_array_off2x2: case AARCH64_OPND_SME_ZA_array_off3_0: case AARCH64_OPND_SME_ZA_array_off3_5: + case AARCH64_OPND_SME_ZA_array_off3x2: case AARCH64_OPND_SME_ZA_array_off4: snprintf (buf, size, "%s[%s, %s%s%s%s%s]", style_reg (styler, "za%s%s", diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index b0084257a94..b925af5ac37 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -140,9 +140,12 @@ enum aarch64_field_kind FLD_cond2, FLD_defgh, FLD_hw, + FLD_imm1_2, FLD_imm1_8, FLD_imm1_10, + FLD_imm1_15, FLD_imm1_16, + FLD_imm2_0, FLD_imm2_8, FLD_imm2_10, FLD_imm2_15, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 434b76c010c..552345d35f6 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5339,6 +5339,22 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("add", 0xc1a11810, 0xffa39c78, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0), SME2_INSN ("add", 0xc120a300, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("add", 0xc120ab00, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), + SME2_INSN ("bfmlal", 0xc1801010, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), + SME2_INSN ("bfmlal", 0xc1901010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("bfmlal", 0xc1909010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("bfmlal", 0xc1200c10, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), + SME2_INSN ("bfmlal", 0xc1200810, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("bfmlal", 0xc1300810, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("bfmlal", 0xc1a00810, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("bfmlal", 0xc1a10810, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("bfmlsl", 0xc1801018, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), + SME2_INSN ("bfmlsl", 0xc1901018, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("bfmlsl", 0xc1909018, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("bfmlsl", 0xc1200c18, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), + SME2_INSN ("bfmlsl", 0xc1200818, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("bfmlsl", 0xc1300818, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("bfmlsl", 0xc1a00818, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("bfmlsl", 0xc1a10818, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), SME2_INSN ("cntp", 0x25208200, 0xff3ffa00, sme_size_22, 0, OP3 (Rd, SME_PNn, SME_VLxN_10), OP_SVE_XV_BHSD, 0, 0), SME2_INSN ("fadd", 0xc1a01c00, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), SME2_INSN ("fadd", 0xc1a11c00, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), @@ -5364,12 +5380,28 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("fmla", 0xc1301800, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0), SME2_INSN ("fmla", 0xc1a01800, 0xffa19c38, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0), SME2_INSN ("fmla", 0xc1a11800, 0xffa39c78, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("fmlal", 0xc1801000, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), + SME2_INSN ("fmlal", 0xc1901000, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("fmlal", 0xc1909000, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("fmlal", 0xc1200c00, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), + SME2_INSN ("fmlal", 0xc1200800, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("fmlal", 0xc1300800, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("fmlal", 0xc1a00800, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("fmlal", 0xc1a10800, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), SME2_INSN ("fmls", 0xc1500010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (2), 0), SME2_INSN ("fmls", 0xc1508010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (4), 0), SME2_INSN ("fmls", 0xc1201808, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0), SME2_INSN ("fmls", 0xc1301808, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0), SME2_INSN ("fmls", 0xc1a01808, 0xffa19c38, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0), SME2_INSN ("fmls", 0xc1a11808, 0xffa39c78, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("fmlsl", 0xc1801008, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), + SME2_INSN ("fmlsl", 0xc1901008, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("fmlsl", 0xc1909008, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("fmlsl", 0xc1200c08, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), + SME2_INSN ("fmlsl", 0xc1200808, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("fmlsl", 0xc1300808, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("fmlsl", 0xc1a00808, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("fmlsl", 0xc1a10808, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), SME2_INSN ("fsub", 0xc1a01c08, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), SME2_INSN ("fsub", 0xc1a11c08, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), SME2_INSN ("ld1b", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0), @@ -5474,6 +5506,22 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("smin", 0xc120a820, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("smin", 0xc120b020, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("smin", 0xc120b820, 0xff23ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_BHSD, 0, 1), + SME2_INSN ("smlal", 0xc1c01000, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), + SME2_INSN ("smlal", 0xc1d01000, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("smlal", 0xc1d09000, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("smlal", 0xc1600c00, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), + SME2_INSN ("smlal", 0xc1600800, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("smlal", 0xc1700800, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("smlal", 0xc1e00800, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("smlal", 0xc1e10800, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("smlsl", 0xc1c01008, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), + SME2_INSN ("smlsl", 0xc1d01008, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("smlsl", 0xc1d09008, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("smlsl", 0xc1600c08, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), + SME2_INSN ("smlsl", 0xc1600808, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("smlsl", 0xc1700808, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("smlsl", 0xc1e00808, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("smlsl", 0xc1e10808, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), SME2_INSN ("sqdmulh", 0xc120a400, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("sqdmulh", 0xc120ac00, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("sqdmulh", 0xc120b400, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1), @@ -5561,6 +5609,22 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("umin", 0xc120a821, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("umin", 0xc120b021, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("umin", 0xc120b821, 0xff23ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_BHSD, 0, 1), + SME2_INSN ("umlal", 0xc1c01010, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), + SME2_INSN ("umlal", 0xc1d01010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("umlal", 0xc1d09010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("umlal", 0xc1600c10, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), + SME2_INSN ("umlal", 0xc1600810, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("umlal", 0xc1700810, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("umlal", 0xc1e00810, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("umlal", 0xc1e10810, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("umlsl", 0xc1c01018, 0xfff01018, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX3_10), OP_SVE_SHH, 0, 0), + SME2_INSN ("umlsl", 0xc1d01018, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("umlsl", 0xc1d09018, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX3_2), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("umlsl", 0xc1600c18, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_SHH, 0, 0), + SME2_INSN ("umlsl", 0xc1600818, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("umlsl", 0xc1700818, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0), + SME2_INSN ("umlsl", 0xc1e00818, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0), + SME2_INSN ("umlsl", 0xc1e10818, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0), SME2_INSN ("urshl", 0xc120a221, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("urshl", 0xc120aa21, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("urshl", 0xc120b221, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1), @@ -6279,10 +6343,14 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \ F(FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \ "an SME horizontal or vertical vector access register") \ + Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off2x2", \ + 2 << OPD_F_OD_LSB, F(FLD_SME_Rv,FLD_imm2_0), "ZA array") \ Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off3_0", 0, \ F(FLD_SME_Rv,FLD_imm3_0), "ZA array") \ Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off3_5", 0, \ F(FLD_SME_Rv,FLD_imm3_5), "ZA array") \ + Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off3x2", \ + 2 << OPD_F_OD_LSB, F(FLD_SME_Rv,FLD_imm3_0), "ZA array") \ Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off4", 0, \ F(FLD_SME_Rv,FLD_imm4_0), "ZA array") \ Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \ @@ -6296,6 +6364,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = F(FLD_SME_Zm, FLD_imm1_10), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX2", 0, \ F(FLD_SME_Zm, FLD_imm2_10), "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zm_INDEX3_2", 0, \ + F(FLD_SME_Zm, FLD_imm2_10, FLD_imm1_2), \ + "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zm_INDEX3_10", 0, \ + F(FLD_SME_Zm, FLD_imm1_15, FLD_imm2_10), \ + "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX1_16", 0, \ F(FLD_SVE_Zn, FLD_imm1_16), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX2_15", 0, \ -- 2.30.2