From ed4fd7b7f30020dfdcd79cfd1e36672395f905d7 Mon Sep 17 00:00:00 2001 From: Anthony Green Date: Wed, 24 Dec 2014 08:37:16 -0500 Subject: [PATCH] Add support for moxie's mul.x and umul.x instructions --- sim/moxie/ChangeLog | 4 ++++ sim/moxie/interp.c | 26 ++++++++++++++++++++++++-- 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/sim/moxie/ChangeLog b/sim/moxie/ChangeLog index d3331c6f13f..561e8c80205 100644 --- a/sim/moxie/ChangeLog +++ b/sim/moxie/ChangeLog @@ -1,3 +1,7 @@ +2014-12-24 Anthony Green + + * interp.c (sim_resume): Add mul.x and umul.x instructions. + 2014-12-12 Anthony Green * interp.c (sim_resume): Add zex instructions. diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c index fdb652850e3..fdd94af859e 100644 --- a/sim/moxie/interp.c +++ b/sim/moxie/interp.c @@ -622,8 +622,30 @@ sim_resume (sd, step, siggnal) cpu.asregs.regs[a] = (int) bv & 0xffff; } break; - case 0x14: /* bad */ - case 0x15: /* bad */ + case 0x14: /* mul.x */ + { + int a = (inst >> 4) & 0xf; + int b = inst & 0xf; + unsigned av = cpu.asregs.regs[a]; + unsigned bv = cpu.asregs.regs[b]; + TRACE("mul.x"); + signed long long r = + (signed long long) av * (signed long long) bv; + cpu.asregs.regs[a] = r >> 32; + } + break; + case 0x15: /* umul.x */ + { + int a = (inst >> 4) & 0xf; + int b = inst & 0xf; + unsigned av = cpu.asregs.regs[a]; + unsigned bv = cpu.asregs.regs[b]; + TRACE("umul.x"); + unsigned long long r = + (unsigned long long) av * (unsigned long long) bv; + cpu.asregs.regs[a] = r >> 32; + } + break; case 0x16: /* bad */ case 0x17: /* bad */ case 0x18: /* bad */ -- 2.30.2