From ed5fd20adb5ffe712d8fdd6513f9405b173dca3e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 26 Jul 2020 14:47:17 +0100 Subject: [PATCH] add nop test cases --- src/soc/simple/test/test_issuer.py | 8 +++++--- src/soc/simulator/program.py | 10 ++++++++-- src/soc/simulator/test_sim.py | 15 ++++++++++++++- 3 files changed, 27 insertions(+), 6 deletions(-) diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index aac3c1ae..58742863 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -154,6 +154,8 @@ class TestRunner(FHDLTestCase): yield pc_i.eq(pc) yield issuer.pc_i.ok.eq(1) + print ("instructions", instructions) + index = sim.pc.CIA.value//4 while index < len(instructions): ins, code = instructions[index] @@ -203,10 +205,10 @@ if __name__ == "__main__": suite = unittest.TestSuite() # suite.addTest(TestRunner(HelloTestCases.test_data)) # suite.addTest(TestRunner(DivTestCase.test_data)) - suite.addTest(TestRunner(AttnTestCase.test_data)) + #suite.addTest(TestRunner(AttnTestCase.test_data)) suite.addTest(TestRunner(GeneralTestCases.test_data)) - suite.addTest(TestRunner(LDSTTestCase().test_data)) - suite.addTest(TestRunner(CRTestCase().test_data)) + #suite.addTest(TestRunner(LDSTTestCase().test_data)) + #suite.addTest(TestRunner(CRTestCase().test_data)) # suite.addTest(TestRunner(ShiftRotTestCase.test_data)) # suite.addTest(TestRunner(LogicalTestCase.test_data)) # suite.addTest(TestRunner(ALUTestCase.test_data)) diff --git a/src/soc/simulator/program.py b/src/soc/simulator/program.py index d77f9d78..1c254c92 100644 --- a/src/soc/simulator/program.py +++ b/src/soc/simulator/program.py @@ -9,6 +9,8 @@ import subprocess import struct import os import sys +from io import BytesIO + filedir = os.path.dirname(os.path.realpath(__file__)) memmap = os.path.join(filedir, "memmap") @@ -26,11 +28,15 @@ class Program: self.endian_fmt = "elf64-little" self.obj_fmt = "-le" - if isinstance(instructions, str): # filename + if isinstance(instructions, bytes): # actual bytes + self.binfile = BytesIO(instructions) + self.binfile.name = "assembly" + self.assembly = '' # noo disassemble number fiiive + elif isinstance(instructions, str): # filename # read instructions into a BytesIO to avoid "too many open files" with open(instructions, "rb") as f: b = f.read() - self.binfile = BytesIO(b, 'rb') + self.binfile = BytesIO(b) self.assembly = '' # noo disassemble number fiiive print("program", self.binfile) else: diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py index b506b4f7..c6a212fd 100644 --- a/src/soc/simulator/test_sim.py +++ b/src/soc/simulator/test_sim.py @@ -205,13 +205,26 @@ class GeneralTestCases(FHDLTestCase): def test_nop(self): lst = ["addi 1, 0, 0x1004", - "nop", + "ori 0,0,0", # "preferred" form of nop "addi 3, 0, 0x15eb", ] initial_regs = [0] * 32 with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 3]) + @unittest.skip("disable") + def test_zero_illegal(self): + lst = bytes([0x10,0x00,0x20,0x39, + 0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0 ]) + disassembly = ["addi 9, 0, 0x10", + "nop", # not quite + "nop"] # not quite + initial_regs = [0] * 32 + with Program(lst, bigendian) as program: + program.assembly = '\n'.join(disassembly) + '\n' # XXX HACK! + self.run_tst_program(program, [1, 3]) + def test_loop(self): """in godbolt.org: register unsigned long i asm ("r12"); -- 2.30.2