From ed72daed06a5178db8a171cae3a6b4e20b65e373 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 27 Jun 2021 12:19:45 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 86740e628..395b732f8 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -472,10 +472,16 @@ Yes, really: CR operations (mtcr, crand, cror) may be Vectorised, predicated, and also pred-result mode applied to it. In this case, the Vectorisation applies to the batch of 4 bits, i.e. it is not the CR individual bits that are treated as the Vector, but the CRs themselves -(CR0, CR8, CR9...) +(CR0, CR8, CR9...). + +Put another way: Vectorised crand uses the higher bits of BA BB BC +to select the CR Field: these will increment sequentially as the Vector +loop progresses, whereas the lower 2 bits (selecting one of eq, ge, le, ov) +remain the same. Thus after each Vectorised operation (crand) a test of the CR result -can in fact be performed. +can in fact be performed. However the only meaningful comparision will +be "eq" or "ne", given that the result is only one bit. # CR Operations -- 2.30.2