From ed7540a46f22151d6c87205df92bc52f5e875130 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 1 Aug 2019 15:10:43 -0700 Subject: [PATCH] Pack P register properly --- passes/pmgen/xilinx_dsp.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index d87d63670..be510b4cb 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -86,14 +86,16 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm) else D = st.ffP->getPort("\\D"); SigSpec Q = st.ffP->getPort("\\Q"); - P.replace(D, Q); - cell->setPort("\\P", Q); + P.replace(pm.sigmap(D), Q); + cell->setPort("\\P", P); cell->setParam("\\PREG", State::S1); if (st.ffP->type == "$dff") cell->setPort("\\CEP", State::S1); else if (st.ffP->type == "$dffe") cell->setPort("\\CEP", st.ffP->getPort("\\EN")); else log_abort(); + + st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P))); } log(" clock: %s (%s)", log_signal(st.clock), "posedge"); -- 2.30.2