From ed7be3e6b68521b2f147034f811a19bd7af86d1a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 17:36:38 -0700 Subject: [PATCH] Add comment --- passes/pmgen/xilinx_srl.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index ce77a3308..71112e3bc 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -218,6 +218,10 @@ struct XilinxSrlPass : public Pass { do { auto pm = xilinx_srl_pm(module, module->selected_cells()); pm.ud_variable.minlen = minlen; + // Since `nusers` does not count module ports as a user, + // and since `sigmap` does not always make such ports + // the canonical signal.. need to maintain a pool these + // ourselves for (auto p : module->ports) { auto w = module->wire(p); if (w->port_output) -- 2.30.2