From eda058f3e9861ab4d439166a83f45360da87f21e Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 5 Jul 2019 20:05:01 +0000 Subject: [PATCH] versa_ecp5: add missing pin directions. Fixes #16. --- nmigen_boards/versa_ecp5.py | 64 ++++++++++++++++++------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/nmigen_boards/versa_ecp5.py b/nmigen_boards/versa_ecp5.py index 6d1c41a..262e309 100644 --- a/nmigen_boards/versa_ecp5.py +++ b/nmigen_boards/versa_ecp5.py @@ -67,52 +67,52 @@ class VersaECP5Platform(LatticeECP5Platform): attrs=Attrs(IO_STANDARD="LVCMOS33") ), - Resource("eth_clk125", 0, Pins("L19"), + Resource("eth_clk125", 0, Pins("L19", dir="i"), Clock(125e6), Attrs(IO_TYPE="LVCMOS25")), - Resource("eth_clk125_pll", 0, Pins("U16"), + Resource("eth_clk125_pll", 0, Pins("U16", dir="i"), Clock(125e6), Attrs(IO_TYPE="LVCMOS25")), # NC by default Resource("eth_rgmii", 0, - Subsignal("rst", PinsN("U17")), - Subsignal("mdc", Pins("T18")), - Subsignal("mdio", Pins("U18")), - Subsignal("tx_clk", Pins("P19")), - Subsignal("tx_ctl", Pins("R20")), - Subsignal("tx_data", Pins("N19 N20 P18 P20")), - Subsignal("rx_clk", Pins("L20")), - Subsignal("rx_ctl", Pins("U19")), - Subsignal("rx_data", Pins("T20 U20 T19 R18")), + Subsignal("rst", PinsN("U17", dir="o")), + Subsignal("mdc", Pins("T18", dir="o")), + Subsignal("mdio", Pins("U18", dir="io")), + Subsignal("tx_clk", Pins("P19", dir="o")), + Subsignal("tx_ctl", Pins("R20", dir="o")), + Subsignal("tx_data", Pins("N19 N20 P18 P20", dir="o")), + Subsignal("rx_clk", Pins("L20", dir="i")), + Subsignal("rx_ctl", Pins("U19", dir="i")), + Subsignal("rx_data", Pins("T20 U20 T19 R18", dir="i")), Attrs(IO_TYPE="LVCMOS25") ), Resource("eth_sgmii", 0, - Subsignal("rst", PinsN("U17"), Attrs(IO_TYPE="LVCMOS25")), - Subsignal("mdc", Pins("T18"), Attrs(IO_TYPE="LVCMOS25")), - Subsignal("mdio", Pins("U18"), Attrs(IO_TYPE="LVCMOS25")), - Subsignal("tx", DiffPairs("W13", "W14")), - Subsignal("rx", DiffPairs("Y14", "Y15")), + Subsignal("rst", PinsN("U17", dir="o"), Attrs(IO_TYPE="LVCMOS25")), + Subsignal("mdc", Pins("T18", dir="o"), Attrs(IO_TYPE="LVCMOS25")), + Subsignal("mdio", Pins("U18", dir="io"), Attrs(IO_TYPE="LVCMOS25")), + Subsignal("tx", DiffPairs("W13", "W14", dir="o")), + Subsignal("rx", DiffPairs("Y14", "Y15", dir="i")), ), - Resource("eth_clk125", 1, Pins("J20"), + Resource("eth_clk125", 1, Pins("J20", dir="i"), Clock(125e6), Attrs(IO_TYPE="LVCMOS25")), - Resource("eth_clk125_pll", 1, Pins("C18"), + Resource("eth_clk125_pll", 1, Pins("C18", dir="i"), Clock(125e6), Attrs(IO_TYPE="LVCMOS25")), # NC by default Resource("eth_rgmii", 1, - Subsignal("rst", PinsN("F20")), - Subsignal("mdc", Pins("G19")), - Subsignal("mdio", Pins("H20")), - Subsignal("tx_clk", Pins("C20")), - Subsignal("tx_ctrl", Pins("E19")), - Subsignal("tx_data", Pins("J17 J16 D19 D20")), - Subsignal("rx_clk", Pins("J19")), - Subsignal("rx_ctrl", Pins("F19")), - Subsignal("rx_data", Pins("G18 G16 H18 H17")), + Subsignal("rst", PinsN("F20", dir="o")), + Subsignal("mdc", Pins("G19", dir="o")), + Subsignal("mdio", Pins("H20", dir="io")), + Subsignal("tx_clk", Pins("C20", dir="o")), + Subsignal("tx_ctrl", Pins("E19", dir="o")), + Subsignal("tx_data", Pins("J17 J16 D19 D20", dir="o")), + Subsignal("rx_clk", Pins("J19", dir="i")), + Subsignal("rx_ctrl", Pins("F19", dir="i")), + Subsignal("rx_data", Pins("G18 G16 H18 H17", dir="i")), Attrs(IO_TYPE="LVCMOS25") ), Resource("eth_sgmii", 1, - Subsignal("rst", PinsN("F20"), Attrs(IO_TYPE="LVCMOS25")), - Subsignal("mdc", Pins("G19"), Attrs(IO_TYPE="LVCMOS25")), - Subsignal("mdio", Pins("H20"), Attrs(IO_TYPE="LVCMOS25")), - Subsignal("tx", DiffPairs("W17", "W18")), - Subsignal("rx", DiffPairs("Y16", "Y17")), + Subsignal("rst", PinsN("F20", dir="o"), Attrs(IO_TYPE="LVCMOS25")), + Subsignal("mdc", Pins("G19", dir="o"), Attrs(IO_TYPE="LVCMOS25")), + Subsignal("mdio", Pins("H20", dir="io"), Attrs(IO_TYPE="LVCMOS25")), + Subsignal("tx", DiffPairs("W17", "W18", dir="o")), + Subsignal("rx", DiffPairs("Y16", "Y17", dir="i")), ), Resource("ddr3", 0, -- 2.30.2