From eda1eadafdd94cd1cb44eb91e7eddfdc0a3888c6 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 29 Mar 2018 14:59:22 +0100
Subject: [PATCH] adding test on migen pinmux

---
 src/migen/safeinmux.py | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/src/migen/safeinmux.py b/src/migen/safeinmux.py
index 75d10e7..3e304e7 100644
--- a/src/migen/safeinmux.py
+++ b/src/migen/safeinmux.py
@@ -18,8 +18,8 @@ class SafeInputMux(Module):
         self.selector = Signal(max=inwidth + 1)
         self.io = set(self.inputs) | set([self.output, self.selector]) 
         sel_r = Signal(max=inwidth + 1)
-        sel25 = Signal(max=1<<inwidth + 1)
-        zero = Constant(0, wlog)
+        sel25 = Signal(max=1<<inwidth)
+        zero = Constant(0)
         muxes = []
         for i in range(len(self.inputs)):
             x = Constant(1<<i, inwidth)
@@ -69,12 +69,20 @@ def tb(dut):
             for sel in [0,1,2,3]:
                 yield dut.selector.eq(sel)
                 yield # run one more clock
+                yield
                 s = ''
+                ins = []
+                for x in range(len(dut.inputs)):
+                    ins.append((yield dut.inputs[x]))
                 for x in range(len(dut.inputs)):
-                    s += ("{0} ".format((yield dut.inputs[x])))
-                print("{0} out={1} sel={2}".format(s, (yield dut.output),
-                                                (yield dut.selector)))
+                    s += ("{0} ".format(ins[x]))
+                sel = (yield dut.selector)
+                out = (yield dut.output)
                 yield
+                print("{0} out={1} sel={2}".format(s, out, sel))
+
+                print ("%d %d" % (out, ins[sel]))
+                #assert out == ins[sel]
 
 
 if __name__ == '__main__':
-- 
2.30.2