From edaa66bbeda28da38eb7cfc9919268bae2d31e66 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 6 Dec 2019 18:20:59 +0100 Subject: [PATCH] boards: add Lambdaconcept's PCIe Screamer (R02) --- litex/boards/platforms/pcie_screamer.py | 96 +++++++++++++++++++++++++ litex/boards/targets/pcie_screamer.py | 81 +++++++++++++++++++++ 2 files changed, 177 insertions(+) create mode 100644 litex/boards/platforms/pcie_screamer.py create mode 100755 litex/boards/targets/pcie_screamer.py diff --git a/litex/boards/platforms/pcie_screamer.py b/litex/boards/platforms/pcie_screamer.py new file mode 100644 index 00000000..d473800b --- /dev/null +++ b/litex/boards/platforms/pcie_screamer.py @@ -0,0 +1,96 @@ +# This file is Copyright (c) 2016-2019 Florent Kermarrec +# This file is Copyright (c) 2019 Pierre-Olivier Vauboin +# License: BSD + + +from migen import * + +from litex.build.generic_platform import * +from litex.build.xilinx import XilinxPlatform + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + ("clk100", 0, Pins("R4"), IOStandard("LVCMOS33")), + + ("user_led", 0, Pins("AB1"), IOStandard("LVCMOS33")), + ("user_led", 1, Pins("AB8"), IOStandard("LVCMOS33")), + + ("user_btn", 0, Pins("AA1"), IOStandard("LVCMOS33")), + ("user_btn", 1, Pins("AB6"), IOStandard("LVCMOS33")), + + ("serial", 0, + Subsignal("tx", Pins("T1")), + Subsignal("rx", Pins("U1")), + IOStandard("LVCMOS33"), + ), + + ("ddram", 0, + Subsignal("a", Pins( + "M2 M5 M3 M1 L6 P1 N3 N2", + "M6 R1 L5 N5 N4 P2 P6"), + IOStandard("SSTL15")), + Subsignal("ba", Pins("L3 K6 L4"), IOStandard("SSTL15")), + Subsignal("ras_n", Pins("J4"), IOStandard("SSTL15")), + Subsignal("cas_n", Pins("K3"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("L1"), IOStandard("SSTL15")), + Subsignal("dm", Pins("G3 F1"), IOStandard("SSTL15")), + Subsignal("dq", Pins( + "G2 H4 H5 J1 K1 H3 H2 J5", + "E3 B2 F3 D2 C2 A1 E2 B1"), + IOStandard("SSTL15"), + Misc("IN_TERM=UNTUNED_SPLIT_50")), + Subsignal("dqs_p", Pins("K2 E1"), IOStandard("DIFF_SSTL15")), + Subsignal("dqs_n", Pins("J2 D1"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_p", Pins("P5"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_n", Pins("P4"), IOStandard("DIFF_SSTL15")), + Subsignal("cke", Pins("J6"), IOStandard("SSTL15")), + Subsignal("odt", Pins("K4"), IOStandard("SSTL15")), + Subsignal("reset_n", Pins("G1"), IOStandard("SSTL15")), + Misc("SLEW=FAST"), + ), + + ("pcie_x1", 0, + Subsignal("rst_n", Pins("AB7"), IOStandard("LVCMOS33")), + Subsignal("clk_p", Pins("F6")), + Subsignal("clk_n", Pins("E6")), + Subsignal("rx_p", Pins("B10")), + Subsignal("rx_n", Pins("A10")), + Subsignal("tx_p", Pins("B6")), + Subsignal("tx_n", Pins("A6")) + ), + + ("usb_fifo_clock", 0, Pins("D17"), IOStandard("LVCMOS33")), + ("usb_fifo", 0, + Subsignal("rst", Pins("K22")), + Subsignal("data", Pins( + "A16 F14 A15 F13 A14 E14 A13 E13", + "B13 C15 C13 C14 B16 E17 B15 F16", + "A20 E18 B20 F18 D19 D21 E19 E21", + "A21 B21 A19 A18 F20 F19 B18 B17")), + Subsignal("be", Pins("K16 L16 G20 H20")), + Subsignal("rxf_n", Pins("M13")), + Subsignal("txe_n", Pins("L13")), + Subsignal("rd_n", Pins("K19")), + Subsignal("wr_n", Pins("M15")), + Subsignal("oe_n", Pins("K18")), + Subsignal("siwua", Pins("M16")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ), +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(XilinxPlatform): + default_clk_name = "clk100" + default_clk_period = 1e9/100e6 + + def __init__(self): + XilinxPlatform.__init__(self, "xc7a35t-fgg484-2", _io, toolchain="vivado") + self.toolchain.bitstream_commands = \ + ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", + "set_property BITSTREAM.CONFIG.CONFIGRATE 40 [current_design]"] + self.toolchain.additional_commands = \ + ["write_cfgmem -force -format bin -interface spix4 -size 16 " + "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] + self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]") diff --git a/litex/boards/targets/pcie_screamer.py b/litex/boards/targets/pcie_screamer.py new file mode 100755 index 00000000..809d051a --- /dev/null +++ b/litex/boards/targets/pcie_screamer.py @@ -0,0 +1,81 @@ +#!/usr/bin/env python3 + +# This file is Copyright (c) 2016-2019 Florent Kermarrec +# License: BSD + +import argparse + +from migen import * + +from litex.boards.platforms import pcie_screamer +from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict + +from litex.soc.cores.clock import * +from litex.soc.integration.soc_sdram import * +from litex.soc.integration.builder import * + +from litedram.modules import MT41K128M16 +from litedram.phy import s7ddrphy + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq): + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) + self.clock_domains.cd_clk200 = ClockDomain() + # # # + + self.submodules.pll = pll = S7PLL(speedgrade=-1) + pll.register_clkin(platform.request("clk100"), 100e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) + pll.create_clkout(self.cd_clk200, 200e6) + + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCSDRAM): + def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): + platform = pcie_screamer.Platform() + + # SoCSDRAM --------------------------------------------------------------------------------- + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, + integrated_rom_size=integrated_rom_size, + integrated_sram_size=0x8000, + **kwargs) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq) + + # DDR3 SDRAM ------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: + self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), + memtype = "DDR3", + nphases = 4, + sys_clk_freq = sys_clk_freq) + self.add_csr("ddrphy") + sdram_module = MT41K128M16(sys_clk_freq, "1:4") + self.register_sdram(self.ddrphy, + geom_settings = sdram_module.geom_settings, + timing_settings = sdram_module.timing_settings) + +# Build -------------------------------------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on PCIe Screamer") + builder_args(parser) + soc_sdram_args(parser) + vivado_build_args(parser) + args = parser.parse_args() + + soc = BaseSoC(**soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build(**vivado_build_argdict(args)) + + +if __name__ == "__main__": + main() -- 2.30.2