From edae5fe3f2474a00a84ae701a3fc6cf19f5d5580 Mon Sep 17 00:00:00 2001 From: David Edelsohn Date: Fri, 27 Jun 2008 08:43:55 -0400 Subject: [PATCH] [multiple changes] 2008-06-27 David Edelsohn * config/rs6000/t-aix52: Append large data option to LDFLAGS for genautomata. 2008-06-27 Edmar Wienskoski * config.gcc (powerpc*-*-*): Add new core e500mc. * config/rs6000/e500mc.md: New file. * config/rs6000/rs6000.c (processor_costs): Add new costs for e500mc. (rs6000_override_options): Add e500mc case to processor_target_table. Altivec and Spe options not allowed with e500mc. Add isel instruction to e500mc by default. Initialize rs6000_cost for e500mc. (rs6000_issue_rate): Set issue rate for e500mc. * config/rs6000/rs6000.h (processor_type): Add PROCESSOR_PPCE500MC. (ASM_CPU_SPEC): Add e500mc. Set TARGET_ISEL to rs6000_isel. * config/rs6000/e500.h: Remove redefinition of TARGET_ISEL. (CHECK_E500_OPTIONS): Remove TARGET_ISEL. * config/rs6000/rs6000.md (define_attr "cpu"): Add ppce500mc.. Include e500mc.md. * doc/invoke.texi: Add e500mc to list of cpus. From-SVN: r137176 --- gcc/ChangeLog | 26 +++++ gcc/config.gcc | 5 +- gcc/config/rs6000/e500.h | 4 +- gcc/config/rs6000/e500mc.md | 200 ++++++++++++++++++++++++++++++++++++ gcc/config/rs6000/rs6000.c | 35 ++++++- gcc/config/rs6000/rs6000.h | 4 +- gcc/config/rs6000/rs6000.md | 3 +- gcc/config/rs6000/t-aix52 | 2 + gcc/doc/invoke.texi | 10 +- 9 files changed, 273 insertions(+), 16 deletions(-) create mode 100644 gcc/config/rs6000/e500mc.md diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2e651a6dc89..394c9c0117b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,29 @@ +2008-06-27 David Edelsohn + + * config/rs6000/t-aix52: Append large data option to LDFLAGS for + genautomata. + +2008-06-27 Edmar Wienskoski + + * config.gcc (powerpc*-*-*): Add new core e500mc. + * config/rs6000/e500mc.md: New file. + * config/rs6000/rs6000.c (processor_costs): Add new costs for + e500mc. + (rs6000_override_options): Add e500mc case to + processor_target_table. Altivec and Spe options not allowed + with e500mc. Add isel instruction to e500mc by + default. Initialize rs6000_cost for e500mc. + (rs6000_issue_rate): Set issue rate for e500mc. + * config/rs6000/rs6000.h (processor_type): Add + PROCESSOR_PPCE500MC. + (ASM_CPU_SPEC): Add e500mc. + Set TARGET_ISEL to rs6000_isel. + * config/rs6000/e500.h: Remove redefinition of TARGET_ISEL. + (CHECK_E500_OPTIONS): Remove TARGET_ISEL. + * config/rs6000/rs6000.md (define_attr "cpu"): Add ppce500mc. + Include e500mc.md. + * doc/invoke.texi: Add e500mc to list of cpus. + 2008-06-27 Laurynas Biveinis PR c/34867 diff --git a/gcc/config.gcc b/gcc/config.gcc index b659fc30b83..f4f171e0c02 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -2819,8 +2819,9 @@ case "${target}" in | rios | rios1 | rios2 | rsc | rsc1 | rs64a \ | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \ | 505 | 601 | 602 | 603 | 603e | ec603e | 604 \ - | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 | e300c[23] \ - | 854[08] | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell) + | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \ + | e300c[23] | 854[08] | e500mc \ + | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell) # OK ;; *) diff --git a/gcc/config/rs6000/e500.h b/gcc/config/rs6000/e500.h index ae909952d8b..c874f08f0ad 100644 --- a/gcc/config/rs6000/e500.h +++ b/gcc/config/rs6000/e500.h @@ -19,7 +19,6 @@ #undef TARGET_SPE_ABI #undef TARGET_SPE #undef TARGET_E500 -#undef TARGET_ISEL #undef TARGET_FPRS #undef TARGET_E500_SINGLE #undef TARGET_E500_DOUBLE @@ -28,13 +27,12 @@ #define TARGET_SPE_ABI rs6000_spe_abi #define TARGET_SPE rs6000_spe #define TARGET_E500 (rs6000_cpu == PROCESSOR_PPC8540) -#define TARGET_ISEL rs6000_isel #define TARGET_FPRS (rs6000_float_gprs == 0) #define TARGET_E500_SINGLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 1) #define TARGET_E500_DOUBLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 2) #define CHECK_E500_OPTIONS \ do { \ - if (TARGET_E500 || TARGET_SPE || TARGET_SPE_ABI || TARGET_ISEL \ + if (TARGET_E500 || TARGET_SPE || TARGET_SPE_ABI \ || TARGET_E500_SINGLE || TARGET_E500_DOUBLE) \ { \ if (TARGET_ALTIVEC) \ diff --git a/gcc/config/rs6000/e500mc.md b/gcc/config/rs6000/e500mc.md new file mode 100644 index 00000000000..86434f95fe1 --- /dev/null +++ b/gcc/config/rs6000/e500mc.md @@ -0,0 +1,200 @@ +;; Pipeline description for Motorola PowerPC e500mc core. +;; Copyright (C) 2008 Free Software Foundation, Inc. +;; Contributed by Edmar Wienskoski (edmar@freescale.com) +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . +;; +;; e500mc 32-bit SU(2), LSU, FPU, BPU +;; Max issue 3 insns/clock cycle (includes 1 branch) +;; FP is half clocked, timings of other instructions are as in the e500v2. + +(define_automaton "e500mc_most,e500mc_long,e500mc_retire") +(define_cpu_unit "e500mc_decode_0,e500mc_decode_1" "e500mc_most") +(define_cpu_unit "e500mc_issue_0,e500mc_issue_1" "e500mc_most") +(define_cpu_unit "e500mc_retire_0,e500mc_retire_1" "e500mc_retire") + +;; SU. +(define_cpu_unit "e500mc_su0_stage0,e500mc_su1_stage0" "e500mc_most") + +;; MU. +(define_cpu_unit "e500mc_mu_stage0,e500mc_mu_stage1" "e500mc_most") +(define_cpu_unit "e500mc_mu_stage2,e500mc_mu_stage3" "e500mc_most") + +;; Non-pipelined division. +(define_cpu_unit "e500mc_mu_div" "e500mc_long") + +;; LSU. +(define_cpu_unit "e500mc_lsu" "e500mc_most") + +;; FPU. +(define_cpu_unit "e500mc_fpu" "e500mc_most") + +;; Branch unit. +(define_cpu_unit "e500mc_bu" "e500mc_most") + +;; The following units are used to make the automata deterministic. +(define_cpu_unit "present_e500mc_decode_0" "e500mc_most") +(define_cpu_unit "present_e500mc_issue_0" "e500mc_most") +(define_cpu_unit "present_e500mc_retire_0" "e500mc_retire") +(define_cpu_unit "present_e500mc_su0_stage0" "e500mc_most") + +;; The following sets to make automata deterministic when option ndfa is used. +(presence_set "present_e500mc_decode_0" "e500mc_decode_0") +(presence_set "present_e500mc_issue_0" "e500mc_issue_0") +(presence_set "present_e500mc_retire_0" "e500mc_retire_0") +(presence_set "present_e500mc_su0_stage0" "e500mc_su0_stage0") + +;; Some useful abbreviations. +(define_reservation "e500mc_decode" + "e500mc_decode_0|e500mc_decode_1+present_e500mc_decode_0") +(define_reservation "e500mc_issue" + "e500mc_issue_0|e500mc_issue_1+present_e500mc_issue_0") +(define_reservation "e500mc_retire" + "e500mc_retire_0|e500mc_retire_1+present_e500mc_retire_0") +(define_reservation "e500mc_su_stage0" + "e500mc_su0_stage0|e500mc_su1_stage0+present_e500mc_su0_stage0") + +;; Simple SU insns. +(define_insn_reservation "e500mc_su" 1 + (and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\ + delayed_compare,var_delayed_compare,fast_compare,\ + shift,trap,var_shift_rotate,cntlz,exts") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire") + +(define_insn_reservation "e500mc_two" 1 + (and (eq_attr "type" "two") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\ + e500mc_issue+e500mc_su_stage0+e500mc_retire") + +(define_insn_reservation "e500mc_three" 1 + (and (eq_attr "type" "three") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\ + e500mc_issue+e500mc_su_stage0+e500mc_retire,\ + e500mc_issue+e500mc_su_stage0+e500mc_retire") + +;; Multiply. +(define_insn_reservation "e500mc_multiply" 4 + (and (eq_attr "type" "imul,imul2,imul3,imul_compare") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_mu_stage0,e500mc_mu_stage1,\ + e500mc_mu_stage2,e500mc_mu_stage3+e500mc_retire") + +;; Divide. We use the average latency time here. +(define_insn_reservation "e500mc_divide" 14 + (and (eq_attr "type" "idiv") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_mu_stage0+e500mc_mu_div,\ + e500mc_mu_div*13") + +;; Branch. +(define_insn_reservation "e500mc_branch" 1 + (and (eq_attr "type" "jmpreg,branch,isync") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_bu,e500mc_retire") + +;; CR logical. +(define_insn_reservation "e500mc_cr_logical" 1 + (and (eq_attr "type" "cr_logical,delayed_cr") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_bu,e500mc_retire") + +;; Mfcr. +(define_insn_reservation "e500mc_mfcr" 1 + (and (eq_attr "type" "mfcr") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire") + +;; Mtcrf. +(define_insn_reservation "e500mc_mtcrf" 1 + (and (eq_attr "type" "mtcr") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire") + +;; Mtjmpr. +(define_insn_reservation "e500mc_mtjmpr" 1 + (and (eq_attr "type" "mtjmpr,mfjmpr") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire") + +;; Brinc. +(define_insn_reservation "e500mc_brinc" 1 + (and (eq_attr "type" "brinc") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire") + +;; Loads. +(define_insn_reservation "e500mc_load" 3 + (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ + load_l,sync") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire") + +(define_insn_reservation "e500mc_fpload" 4 + (and (eq_attr "type" "fpload,fpload_ux,fpload_u") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_lsu,nothing*2,e500mc_retire") + +;; Stores. +(define_insn_reservation "e500mc_store" 3 + (and (eq_attr "type" "store,store_ux,store_u,store_c") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire") + +(define_insn_reservation "e500mc_fpstore" 3 + (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire") + +;; The following ignores the retire unit to avoid a large automata. + +;; Simple FP. +(define_insn_reservation "e500mc_simple_float" 8 + (and (eq_attr "type" "fpsimple") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_fpu") +; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire") + +;; FP. +(define_insn_reservation "e500mc_float" 8 + (and (eq_attr "type" "fp") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_fpu") +; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire") + +(define_insn_reservation "e500mc_fpcompare" 8 + (and (eq_attr "type" "fpcompare") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_fpu") + +(define_insn_reservation "e500mc_dmul" 10 + (and (eq_attr "type" "dmul") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_fpu") + +;; FP divides are not pipelined. +(define_insn_reservation "e500mc_sdiv" 36 + (and (eq_attr "type" "sdiv") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*35") + +(define_insn_reservation "e500mc_ddiv" 66 + (and (eq_attr "type" "ddiv") + (eq_attr "cpu" "ppce500mc")) + "e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*65") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 5fd021d2fa5..904587d68dd 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -694,6 +694,25 @@ struct processor_costs ppce300c2c3_cost = { 1, /* prefetch streams /*/ }; +/* Instruction costs on PPCE500MC processors. */ +static const +struct processor_costs ppce500mc_cost = { + COSTS_N_INSNS (4), /* mulsi */ + COSTS_N_INSNS (4), /* mulsi_const */ + COSTS_N_INSNS (4), /* mulsi_const9 */ + COSTS_N_INSNS (4), /* muldi */ + COSTS_N_INSNS (14), /* divsi */ + COSTS_N_INSNS (14), /* divdi */ + COSTS_N_INSNS (8), /* fp */ + COSTS_N_INSNS (10), /* dmul */ + COSTS_N_INSNS (36), /* sdiv */ + COSTS_N_INSNS (66), /* ddiv */ + 64, /* cache line size */ + 32, /* l1 cache */ + 128, /* l2 cache */ + 1, /* prefetch streams /*/ +}; + /* Instruction costs on POWER4 and POWER5 processors. */ static const struct processor_costs power4_cost = { @@ -1456,6 +1475,7 @@ rs6000_override_options (const char *default_cpu) {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN}, {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK}, + {"e500mc", PROCESSOR_PPCE500MC, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, {"970", PROCESSOR_POWER4, POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, @@ -1559,10 +1579,12 @@ rs6000_override_options (const char *default_cpu) } } - if (TARGET_E500 && !rs6000_explicit_options.isel) + if ((TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC) + && !rs6000_explicit_options.isel) rs6000_isel = 1; - if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3) + if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3 + || rs6000_cpu == PROCESSOR_PPCE500MC) { if (TARGET_ALTIVEC) error ("AltiVec not supported in this target"); @@ -1679,9 +1701,9 @@ rs6000_override_options (const char *default_cpu) SUB3TARGET_OVERRIDE_OPTIONS; #endif - if (TARGET_E500) + if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC) { - /* The e500 does not have string instructions, and we set + /* The e500 and e500mc do not have string instructions, and we set MASK_STRING above when optimizing for size. */ if ((target_flags & MASK_STRING) != 0) target_flags = target_flags & ~MASK_STRING; @@ -1894,6 +1916,10 @@ rs6000_override_options (const char *default_cpu) rs6000_cost = &ppce300c2c3_cost; break; + case PROCESSOR_PPCE500MC: + rs6000_cost = &ppce500mc_cost; + break; + case PROCESSOR_POWER4: case PROCESSOR_POWER5: rs6000_cost = &power4_cost; @@ -19008,6 +19034,7 @@ rs6000_issue_rate (void) case CPU_CELL: case CPU_PPCE300C2: case CPU_PPCE300C3: + case CPU_PPCE500MC: return 2; case CPU_RIOS2: case CPU_PPC604: diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 4c225a3f0e7..8a926e43c44 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -133,6 +133,7 @@ %{mcpu=8548: -me500} \ %{mcpu=e300c2: -me300} \ %{mcpu=e300c3: -me300} \ +%{mcpu=e500mc: -me500mc} \ %{maltivec: -maltivec} \ -many" @@ -282,6 +283,7 @@ enum processor_type PROCESSOR_PPC8540, PROCESSOR_PPCE300C2, PROCESSOR_PPCE300C3, + PROCESSOR_PPCE500MC, PROCESSOR_POWER4, PROCESSOR_POWER5, PROCESSOR_POWER6, @@ -400,7 +402,7 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops; #define TARGET_SPE_ABI 0 #define TARGET_SPE 0 #define TARGET_E500 0 -#define TARGET_ISEL 0 +#define TARGET_ISEL rs6000_isel #define TARGET_FPRS 1 #define TARGET_E500_SINGLE 0 #define TARGET_E500_DOUBLE 0 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 461eda7c6a5..5efde36de8d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -133,7 +133,7 @@ ;; Processor type -- this attribute must exactly match the processor_type ;; enumeration in rs6000.h. -(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,power4,power5,power6,cell" +(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,cell" (const (symbol_ref "rs6000_cpu_attr"))) @@ -167,6 +167,7 @@ (include "7450.md") (include "8540.md") (include "e300c2c3.md") +(include "e500mc.md") (include "power4.md") (include "power5.md") (include "power6.md") diff --git a/gcc/config/rs6000/t-aix52 b/gcc/config/rs6000/t-aix52 index 37a5d83b828..3b19cbcee44 100644 --- a/gcc/config/rs6000/t-aix52 +++ b/gcc/config/rs6000/t-aix52 @@ -55,3 +55,5 @@ TARGET_LIBGCC2_CFLAGS = -mlong-double-128 # Either 32-bit and 64-bit objects in archives. AR_FLAGS_FOR_TARGET = -X32_64 +# genautomata requires more than 256MB of data +build/genautomata : override LDFLAGS += -Wl,-bmaxdata:0x20000000 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f69f0019dec..c59d88e492d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -13011,11 +13011,11 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823}, @samp{860}, @samp{970}, @samp{8540}, @samp{e300c2}, @samp{e300c3}, -@samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{power}, -@samp{power2}, @samp{power3}, @samp{power4}, @samp{power5}, -@samp{power5+}, @samp{power6}, @samp{power6x}, @samp{common}, -@samp{powerpc}, @samp{powerpc64}, @samp{rios}, @samp{rios1}, -@samp{rios2}, @samp{rsc}, and @samp{rs64}. +@samp{e500mc}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, +@samp{power}, @samp{power2}, @samp{power3}, @samp{power4}, +@samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, +@samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios}, +@samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}. @option{-mcpu=common} selects a completely generic processor. Code generated under this option will run on any POWER or PowerPC processor. -- 2.30.2