From edb1731ef98a35262e838cfbf08b75a611843bf5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 1 Nov 2019 11:30:50 +0100 Subject: [PATCH] soc_core/soc_core_args: specify default cpu (vexriscv) --- litex/soc/integration/soc_core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 346175f0..1a811ff7 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -540,7 +540,7 @@ class SoCCore(Module): def soc_core_args(parser): # CPU parameters parser.add_argument("--cpu-type", default=None, - help="select CPU: {}".format(", ".join(iter(cpu.CPUS.keys())))) + help="select CPU: {}, (default=vexriscv)".format(", ".join(iter(cpu.CPUS.keys())))) parser.add_argument("--cpu-variant", default=None, help="select CPU variant, (default=standard)") parser.add_argument("--cpu-reset-address", default=None, type=int, -- 2.30.2