From edbdd29a4cf38f2e2b32f0f48d70d63940394e5a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 19 Jun 2020 17:49:32 +0100 Subject: [PATCH] add divide-by-zero test to test_div_sim.py --- src/soc/simulator/test_div_sim.py | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/soc/simulator/test_div_sim.py b/src/soc/simulator/test_div_sim.py index 2129de33..acaeed7a 100644 --- a/src/soc/simulator/test_div_sim.py +++ b/src/soc/simulator/test_div_sim.py @@ -32,7 +32,15 @@ class DivTestCases(FHDLTestCase): with Program(lst) as program: self.run_tst_program(program, [1, 2, 3]) - def test_0_moduw(self): + def test_1_divw_byzero(self): + lst = ["addi 1, 0, 0x5678", + "addi 2, 0, 0x0", + "divw 3, 1, 2", + ] + with Program(lst) as program: + self.run_tst_program(program, [1, 2, 3]) + + def test_2_moduw(self): lst = ["addi 1, 0, 0x5678", "addi 2, 0, 0x1234", "moduw 3, 1, 2", -- 2.30.2