From ee049f6b717ea6e20cef38f16a8024276b181d17 Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Tue, 22 May 2018 10:21:29 +0200 Subject: [PATCH] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits We are now using these bits, so don't assert that they are not set. In gen8, if these bits are set compaction is not possible. On gen9 and CHV platforms set_3src_control_index() checks these bits (and others) against a table to validate if the particular bit combination is eligible for compaction or not. v2 - Add more detail in the commit message explaining the situation for SKL+ and CHV (Jason) Reviewed-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand Reviewed-by: Matt Turner --- src/intel/compiler/brw_eu_compact.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_eu_compact.c b/src/intel/compiler/brw_eu_compact.c index 51dce9efbdd..daebdca8e37 100644 --- a/src/intel/compiler/brw_eu_compact.c +++ b/src/intel/compiler/brw_eu_compact.c @@ -928,8 +928,11 @@ has_3src_unmapped_bits(const struct gen_device_info *devinfo, assert(!brw_inst_bits(src, 127, 126) && !brw_inst_bits(src, 105, 105) && !brw_inst_bits(src, 84, 84) && - !brw_inst_bits(src, 36, 35) && !brw_inst_bits(src, 7, 7)); + + /* Src1Type and Src2Type, used for mixed-precision floating point */ + if (brw_inst_bits(src, 36, 35)) + return true; } return false; -- 2.30.2