From ee0ce878679467b4edbf0a592c70978329aaa416 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 26 Oct 2020 16:46:20 +0000 Subject: [PATCH] --- openpower/sv/predication.mdwn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openpower/sv/predication.mdwn b/openpower/sv/predication.mdwn index bae1dd12d..c5bd20a12 100644 --- a/openpower/sv/predication.mdwn +++ b/openpower/sv/predication.mdwn @@ -35,7 +35,9 @@ new vector-related instructions unless essential or compelling. All other proposals utilise existing scalar opcodes which already happen to have bitmanipulation, arithmetic, and inter-file transfer capability (mfcr, mfspr etc). They also involve adding extra bitmanip opcodes, such that by utilising those scalar registers as predicate masks SV achieves "par" with other Cray-style Vector ISAs, all without actually having to add any actual Vector opcodes. -Adding special opcodes just for manipulating predicate masks is anomalous, costly, and unnecessary. +In addition those bitmanip operations, although some of them are obscure and unusual in the scalar world, do actually have practical applicatiobe outside of a vector context. + +Adding a full set special vector opcodes just for manipulating predicate masks and being able to transfer them to other regfiles (a la mfcr) is however anomalous, costly, and unnecessary. ## CR-based predication proposal -- 2.30.2