From ee1ba7d00f361e32e9ed2447f421c80be4315ddb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 6 Jul 2020 14:12:12 +0100 Subject: [PATCH] adding mtspr tests --- libreriscv | 2 +- .../fu/compunits/test/test_alu_compunit.py | 6 ++-- .../fu/compunits/test/test_branch_compunit.py | 2 +- src/soc/fu/compunits/test/test_compunit.py | 14 ++++---- src/soc/fu/compunits/test/test_cr_compunit.py | 2 +- .../compunits/test/test_logical_compunit.py | 2 +- .../compunits/test/test_shiftrot_compunit.py | 2 +- .../fu/compunits/test/test_spr_compunit.py | 19 ++++++++--- .../fu/compunits/test/test_trap_compunit.py | 2 +- src/soc/fu/spr/test/test_pipe_caller.py | 26 ++++++++++++--- src/soc/fu/test/common.py | 32 ++++++++++++++++++- src/soc/fu/trap/test/test_pipe_caller.py | 2 +- 12 files changed, 85 insertions(+), 26 deletions(-) diff --git a/libreriscv b/libreriscv index 3cde5558..1bfe6d5b 160000 --- a/libreriscv +++ b/libreriscv @@ -1 +1 @@ -Subproject commit 3cde5558a3df42b4a08be86881b03dbbdf5ea3e2 +Subproject commit 1bfe6d5bd723b78bd694a1f0955f1982f453196d diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py index e517192c..d58dc61e 100644 --- a/src/soc/fu/compunits/test/test_alu_compunit.py +++ b/src/soc/fu/compunits/test/test_alu_compunit.py @@ -20,7 +20,7 @@ class ALUTestRunner(TestRunner): res = yield from get_cu_inputs(dec2, sim) return res - def check_cu_outputs(self, res, dec2, sim, code): + def check_cu_outputs(self, res, dec2, sim, alu, code): """naming (res) must conform to ALUFunctionUnit output regspec """ @@ -39,9 +39,9 @@ class ALUTestRunner(TestRunner): yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_xer_ov(sim_o, sim, alu, dec2) yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_xer_so(sim_o, sim, alu, dec2) ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) ALUHelpers.check_xer_ov(self, res, sim_o, code) diff --git a/src/soc/fu/compunits/test/test_branch_compunit.py b/src/soc/fu/compunits/test/test_branch_compunit.py index 6c9d1f6d..31e664c5 100644 --- a/src/soc/fu/compunits/test/test_branch_compunit.py +++ b/src/soc/fu/compunits/test/test_branch_compunit.py @@ -25,7 +25,7 @@ class BranchTestRunner(TestRunner): res = yield from get_cu_inputs(dec2, sim) return res - def check_cu_outputs(self, res, dec2, sim, code): + def check_cu_outputs(self, res, dec2, sim, alu, code): """naming (res) must conform to BranchFunctionUnit output regspec """ diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index b1ee7c6f..8b21029f 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -9,7 +9,7 @@ from soc.decoder.power_enums import Function from soc.decoder.isa.all import ISA from soc.experiment.compalu_multi import find_ok # hack - +from soc.config.test.test_loadstore import TestMemPspec def set_cu_input(cu, idx, data): rdop = cu.get_in_name(idx) @@ -169,11 +169,13 @@ class TestRunner(FHDLTestCase): if self.funit == Function.LDST: from soc.experiment.l0_cache import TstL0CacheBuffer - m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64, - addrwid=3, - ifacetype='test_bare_wb') + pspec = TestMemPspec(ldst_ifacetype='test_bare_wb', + addr_wid=48, + mask_wid=8, + reg_wid=64) + m.submodules.l0 = l0 = TstL0CacheBuffer(pspec, n_units=1) pi = l0.l0.dports[0] - m.submodules.cu = cu = self.fukls(pi, awid=3) + m.submodules.cu = cu = self.fukls(pi, idx=0, awid=3) m.d.comb += cu.ad.go.eq(cu.ad.rel) # link addr-go direct to rel m.d.comb += cu.st.go.eq(cu.st.rel) # link store-go direct to rel else: @@ -284,7 +286,7 @@ class TestRunner(FHDLTestCase): yield from dump_sim_memory(self, l0, sim, code) yield from self.iodef.check_cu_outputs(res, pdecode2, - sim, code) + sim, cu.alu, code) # sigh. hard-coded. test memory if self.funit == Function.LDST: diff --git a/src/soc/fu/compunits/test/test_cr_compunit.py b/src/soc/fu/compunits/test/test_cr_compunit.py index 6271ab09..9d05d3f7 100644 --- a/src/soc/fu/compunits/test/test_cr_compunit.py +++ b/src/soc/fu/compunits/test/test_cr_compunit.py @@ -20,7 +20,7 @@ class CRTestRunner(TestRunner): res = yield from get_cu_inputs(dec2, sim) return res - def check_cu_outputs(self, res, dec2, sim, code): + def check_cu_outputs(self, res, dec2, sim, alu, code): """naming (res) must conform to CRFunctionUnit output regspec """ diff --git a/src/soc/fu/compunits/test/test_logical_compunit.py b/src/soc/fu/compunits/test/test_logical_compunit.py index d7465e79..439901a5 100644 --- a/src/soc/fu/compunits/test/test_logical_compunit.py +++ b/src/soc/fu/compunits/test/test_logical_compunit.py @@ -19,7 +19,7 @@ class LogicalTestRunner(TestRunner): res = yield from get_cu_inputs(dec2, sim) return res - def check_cu_outputs(self, res, dec2, sim, code): + def check_cu_outputs(self, res, dec2, sim, alu, code): """naming (res) must conform to LogicalFunctionUnit output regspec """ diff --git a/src/soc/fu/compunits/test/test_shiftrot_compunit.py b/src/soc/fu/compunits/test/test_shiftrot_compunit.py index af14910b..1b8bf770 100644 --- a/src/soc/fu/compunits/test/test_shiftrot_compunit.py +++ b/src/soc/fu/compunits/test/test_shiftrot_compunit.py @@ -20,7 +20,7 @@ class ShiftRotTestRunner(TestRunner): res = yield from get_cu_inputs(dec2, sim) return res - def check_cu_outputs(self, res, dec2, sim, code): + def check_cu_outputs(self, res, dec2, sim, alu, code): """naming (res) must conform to ShiftRotFunctionUnit output regspec """ diff --git a/src/soc/fu/compunits/test/test_spr_compunit.py b/src/soc/fu/compunits/test/test_spr_compunit.py index 23366c53..087fc508 100644 --- a/src/soc/fu/compunits/test/test_spr_compunit.py +++ b/src/soc/fu/compunits/test/test_spr_compunit.py @@ -20,7 +20,7 @@ class SPRTestRunner(TestRunner): res = yield from get_cu_inputs(dec2, sim) return res - def check_cu_outputs(self, res, dec2, sim, code): + def check_cu_outputs(self, res, dec2, sim, alu, code): """naming (res) must conform to SPRFunctionUnit output regspec """ @@ -37,19 +37,30 @@ class SPRTestRunner(TestRunner): sim_o = {} + yield from ALUHelpers.get_int_o(res, alu, dec2) + yield from ALUHelpers.get_fast_spr1(res, alu, dec2) + yield from ALUHelpers.get_slow_spr1(res, alu, dec2) + yield from ALUHelpers.get_xer_ov(res, alu, dec2) + yield from ALUHelpers.get_xer_ca(res, alu, dec2) + yield from ALUHelpers.get_xer_so(res, alu, dec2) + + print ("output", res) + yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) - yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_xer_so(sim_o, sim, alu, dec2) + yield from ALUHelpers.get_wr_sim_xer_ov(sim_o, sim, alu, dec2) yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2) yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2) yield from ALUHelpers.get_wr_slow_spr1(sim_o, sim, dec2) + print ("sim output", sim_o) + ALUHelpers.check_xer_ov(self, res, sim_o, code) ALUHelpers.check_xer_ca(self, res, sim_o, code) + ALUHelpers.check_xer_so(self, res, sim_o, code) ALUHelpers.check_int_o(self, res, sim_o, code) ALUHelpers.check_fast_spr1(self, res, sim_o, code) ALUHelpers.check_slow_spr1(self, res, sim_o, code) - ALUHelpers.check_xer_so(self, res, sim_o, code) if __name__ == "__main__": diff --git a/src/soc/fu/compunits/test/test_trap_compunit.py b/src/soc/fu/compunits/test/test_trap_compunit.py index 4f4b44d3..86ea9478 100644 --- a/src/soc/fu/compunits/test/test_trap_compunit.py +++ b/src/soc/fu/compunits/test/test_trap_compunit.py @@ -20,7 +20,7 @@ class TrapTestRunner(TestRunner): res = yield from get_cu_inputs(dec2, sim) return res - def check_cu_outputs(self, res, dec2, sim, code): + def check_cu_outputs(self, res, dec2, sim, alu, code): """naming (res) must conform to TrapFunctionUnit output regspec """ diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py index ebe5d884..be147ca7 100644 --- a/src/soc/fu/spr/test/test_pipe_caller.py +++ b/src/soc/fu/spr/test/test_pipe_caller.py @@ -85,9 +85,23 @@ class SPRTestCase(FHDLTestCase): def test_1_mfspr(self): lst = ["mfspr 1, 26", # SRR0 "mfspr 2, 27", # SRR1 - "mfspr 2, 8",] # LR + "mfspr 3, 8", # LR + "mfspr 4, 1",] # XER initial_regs = [0] * 32 - initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234} + initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234, + 'XER': 0xe00c0000} + self.run_tst_program(Program(lst), initial_regs, initial_sprs) + + def test_1_mtspr(self): + lst = ["mtspr 26, 1", # SRR0 + "mtspr 27, 2", # and into reg 2 + "mtspr 1, 3",] # XER + initial_regs = [0] * 32 + initial_regs[1] = 0x129518230011feed + initial_regs[2] = 0x129518230011feed + initial_regs[3] = 0xe00c0000 + initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234, + 'XER': 0x0} self.run_tst_program(Program(lst), initial_regs, initial_sprs) def test_ilang(self): @@ -206,18 +220,20 @@ class TestRunner(FHDLTestCase): print ("output", res) yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) - yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_xer_so(sim_o, sim, alu, dec2) + yield from ALUHelpers.get_wr_sim_xer_ov(sim_o, sim, alu, dec2) yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2) yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2) yield from ALUHelpers.get_wr_slow_spr1(sim_o, sim, dec2) + print ("sim output", sim_o) + ALUHelpers.check_xer_ov(self, res, sim_o, code) ALUHelpers.check_xer_ca(self, res, sim_o, code) + ALUHelpers.check_xer_so(self, res, sim_o, code) ALUHelpers.check_int_o(self, res, sim_o, code) ALUHelpers.check_fast_spr1(self, res, sim_o, code) ALUHelpers.check_slow_spr1(self, res, sim_o, code) - ALUHelpers.check_xer_so(self, res, sim_o, code) if __name__ == "__main__": diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py index 0b8dd58f..b07b3885 100644 --- a/src/soc/fu/test/common.py +++ b/src/soc/fu/test/common.py @@ -233,6 +233,8 @@ class ALUHelpers: oe = yield dec2.e.do.oe.oe oe_ok = yield dec2.e.do.oe.ok xer_out = yield dec2.e.xer_out + if not (yield alu.n.data_o.xer_so.ok): + return if xer_out or (oe and oe_ok): res['xer_so'] = yield alu.n.data_o.xer_so.data[0] @@ -240,12 +242,16 @@ class ALUHelpers: oe = yield dec2.e.do.oe.oe oe_ok = yield dec2.e.do.oe.ok xer_out = yield dec2.e.xer_out + if not (yield alu.n.data_o.xer_ov.ok): + return if xer_out or (oe and oe_ok): res['xer_ov'] = yield alu.n.data_o.xer_ov.data def get_xer_ca(res, alu, dec2): cry_out = yield dec2.e.do.output_carry xer_out = yield dec2.e.xer_out + if not (yield alu.n.data_o.xer_ca.ok): + return if xer_out or (cry_out): res['xer_ca'] = yield alu.n.data_o.xer_ca.data @@ -291,12 +297,36 @@ class ALUHelpers: res['spr1'] = sim.spr[spr_name].value def get_wr_sim_xer_ca(res, sim, dec2): + #if not (yield alu.n.data_o.xer_ca.ok): + # return cry_out = yield dec2.e.do.output_carry - if cry_out: + xer_out = yield dec2.e.xer_out + if cry_out or xer_out: expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0 expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0 res['xer_ca'] = expected_carry | (expected_carry32 << 1) + def get_wr_sim_xer_ov(res, sim, alu, dec2): + oe = yield dec2.e.do.oe.oe + oe_ok = yield dec2.e.do.oe.ok + xer_out = yield dec2.e.xer_out + print ("get_wr_sim_xer_ov", xer_out) + if not (yield alu.n.data_o.xer_ov.ok): + return + if xer_out or (oe and oe_ok): + expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0 + expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0 + res['xer_ov'] = expected_ov | (expected_ov32 << 1) + + def get_wr_sim_xer_so(res, sim, alu, dec2): + oe = yield dec2.e.do.oe.oe + oe_ok = yield dec2.e.do.oe.ok + xer_out = yield dec2.e.xer_out + if not (yield alu.n.data_o.xer_so.ok): + return + if xer_out or (oe and oe_ok): + res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0 + def get_sim_xer_ov(res, sim, dec2): oe = yield dec2.e.do.oe.oe oe_ok = yield dec2.e.do.oe.ok diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py index b53f935f..25514730 100644 --- a/src/soc/fu/trap/test/test_pipe_caller.py +++ b/src/soc/fu/trap/test/test_pipe_caller.py @@ -113,7 +113,7 @@ class TrapTestCase(FHDLTestCase): initial_regs[1] = 0xffffffffffffffff self.run_tst_program(Program(lst), initial_regs) - def test_2_mtmsr_1(self): + def test_3_mtmsr_1(self): lst = ["mtmsr 1,1"] initial_regs = [0] * 32 initial_regs[1] = 0xffffffffffffffff -- 2.30.2