From ee3eb545462b0f11404e317762e1519b9168015b Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 5 May 2022 14:46:39 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index fa4ccd2d9..11e6b8b62 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -17,10 +17,15 @@ task? Hints as to the answer emerge from an article "[SIMD considered harmful](https://www.sigarch.org/simd-instructions-considered-harmful/)" which illustrates a catastrophic rabbit-hole taken by Industry Giants -since the 90s (over 3 decades) whereby SIMD width, an Order(N^6) opcode +ARM, Intel, AMD, +since the 90s (over 3 decades) whereby SIMD, an Order(N^6) opcode proliferation nightmare, with its mantra "make it easy for hardware engineers, let software sort out the mess" literally overwhelming programmers. Worse than that, specialists in charging clients Optimisation Services are finding that AVX-512, to take an example, is anything but optimal: overall performance actually *decreases* even as power consumption goes up. + +Cray-style Vectors solved, over thirty years ago, the opcode proliferation +nightmare. Only the NEC SX Aurora however truly kept the Cray Vector flame +alive, until RISC-V RVV and now SVP64 and recently MRISC32 joined it. -- 2.30.2