From ee40b04429bbf86e94579b11e29b7ece7b3c08a9 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Mon, 6 Jul 2015 18:43:33 +0200 Subject: [PATCH] i386.md (extv): Rename from extv. * config/i386/i386.md (extv): Rename from extv. Use SWI24 modes for operands 0 and 1. Use SImode for operands 2 and 3. Copy operand 1 to a temporary if !ext_register_operand. Remove ancient extract_bit_field workaround. (*extv): Rename from *mov_extv_1. (*extvqi): Rename from *movqi_extv_q. (extzv): Rename from extzv. Use SWI248 modes for operands 0 and 1. Use SImode for operands 2 and 3. Copy operand 1 to a temporary if !ext_register_operand. Remove ancient extract_bit_field workaround. (*extzv): Rename from *mov_extzv_1. (*extzvqi): Rename from *movqi_extzv_1. (*testqi_ext_3): Remove modes from const_int_operand predicated operands. Add "n" constraint. (*btsq, *btrq, *btcq): Remove mode from const_0_to_63 predicated operand. Add "J" constraint. (*btsq, *btrq, *btcq peephole2s): Remove mode from const_0_to_63 predicated operand. (regmode): New insn attribute. (*bt): Use SImode for operand 1. Change operand 1 predicate to nonmemory_operand. Use regmode insn attribute. (*jcc_bt_1): Convert operand 2 to SImode. (*jcc_bt_mask): Remove mode from operand 3. (*jcc_btsi_1, *jcc_btsi_mask_1): Remove patterns. (tbm_bextri_): Remove modes from const_0_to_255 predicated operands. Use "N" constraint instead of "n". From-SVN: r225463 --- gcc/ChangeLog | 29 ++++++ gcc/config/i386/i386.md | 201 ++++++++++++---------------------------- 2 files changed, 89 insertions(+), 141 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 82755498c17..b9785156595 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,32 @@ +2015-07-06 Uros Bizjak + + * config/i386/i386.md (extv): Rename from extv. Use SWI24 + modes for operands 0 and 1. Use SImode for operands 2 and 3. + Copy operand 1 to a temporary if !ext_register_operand. Remove + ancient extract_bit_field workaround. + (*extv): Rename from *mov_extv_1. + (*extvqi): Rename from *movqi_extv_q. + (extzv): Rename from extzv. Use SWI248 modes for + operands 0 and 1. Use SImode for operands 2 and 3. Copy operand 1 + to a temporary if !ext_register_operand. Remove ancient + extract_bit_field workaround. + (*extzv): Rename from *mov_extzv_1. + (*extzvqi): Rename from *movqi_extzv_1. + (*testqi_ext_3): Remove modes from const_int_operand predicated + operands. Add "n" constraint. + (*btsq, *btrq, *btcq): Remove mode from const_0_to_63 predicated + operand. Add "J" constraint. + (*btsq, *btrq, *btcq peephole2s): Remove mode from + const_0_to_63 predicated operand. + (regmode): New insn attribute. + (*bt): Use SImode for operand 1. Change operand 1 predicate + to nonmemory_operand. Use regmode insn attribute. + (*jcc_bt_1): Convert operand 2 to SImode. + (*jcc_bt_mask): Remove mode from operand 3. + (*jcc_btsi_1, *jcc_btsi_mask_1): Remove patterns. + (tbm_bextri_): Remove modes from const_0_to_255 predicated + operands. Use "N" constraint instead of "n". + 2015-07-06 Alan Lawrence * config/arm/arm.md (movdi): Avoid odd-number ldrd/strd in ARM state. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index ff7baa4b66f..f59b2f8f819 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -2675,7 +2675,22 @@ (set_attr "mode" "") (set_attr "length_immediate" "0")]) -(define_insn "*mov_extv_1" +(define_expand "extv" + [(set (match_operand:SWI24 0 "register_operand") + (sign_extract:SWI24 (match_operand:SWI24 1 "register_operand") + (match_operand:SI 2 "const_int_operand") + (match_operand:SI 3 "const_int_operand")))] + "" +{ + /* Handle extractions from %ah et al. */ + if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8) + FAIL; + + if (! ext_register_operand (operands[1], VOIDmode)) + operands[1] = copy_to_reg (operands[1]); +}) + +(define_insn "*extv" [(set (match_operand:SWI24 0 "register_operand" "=R") (sign_extract:SWI24 (match_operand 1 "ext_register_operand" "Q") (const_int 8) @@ -2685,7 +2700,7 @@ [(set_attr "type" "imovx") (set_attr "mode" "SI")]) -(define_insn "*movqi_extv_1" +(define_insn "*extvqi" [(set (match_operand:QI 0 "nonimmediate_x64nomem_operand" "=Q,?R,m") (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q,Q") (const_int 8) @@ -2712,17 +2727,32 @@ (const_string "SI") (const_string "QI")))]) -(define_insn "*mov_extzv_1" - [(set (match_operand:SWI48 0 "register_operand" "=R") - (zero_extract:SWI48 (match_operand 1 "ext_register_operand" "Q") - (const_int 8) - (const_int 8)))] +(define_expand "extzv" + [(set (match_operand:SWI248 0 "register_operand") + (zero_extract:SWI248 (match_operand:SWI248 1 "register_operand") + (match_operand:SI 2 "const_int_operand") + (match_operand:SI 3 "const_int_operand")))] + "" +{ + /* Handle extractions from %ah et al. */ + if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8) + FAIL; + + if (! ext_register_operand (operands[1], VOIDmode)) + operands[1] = copy_to_reg (operands[1]); +}) + +(define_insn "*extzv" + [(set (match_operand:SWI248 0 "register_operand" "=R") + (zero_extract:SWI248 (match_operand 1 "ext_register_operand" "Q") + (const_int 8) + (const_int 8)))] "" "movz{bl|x}\t{%h1, %k0|%k0, %h1}" [(set_attr "type" "imovx") (set_attr "mode" "SI")]) -(define_insn "*movqi_extzv_2" +(define_insn "*extzvqi" [(set (match_operand:QI 0 "nonimmediate_x64nomem_operand" "=Q,?R,m") (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q,Q") @@ -2752,8 +2782,8 @@ (define_insn "mov_insv_1" [(set (zero_extract:SWI48 (match_operand 0 "ext_register_operand" "+Q,Q") - (const_int 8) - (const_int 8)) + (const_int 8) + (const_int 8)) (match_operand:SWI48 1 "general_x64nomem_operand" "Qn,m"))] "" { @@ -7583,8 +7613,8 @@ [(set (reg FLAGS_REG) (compare (zero_extract:SWI48 (match_operand 0 "nonimmediate_operand" "rm") - (match_operand:SWI48 1 "const_int_operand") - (match_operand:SWI48 2 "const_int_operand")) + (match_operand 1 "const_int_operand" "n") + (match_operand 2 "const_int_operand" "n")) (const_int 0)))] "ix86_match_ccmode (insn, CCNOmode) && ((TARGET_64BIT && GET_MODE (operands[0]) == DImode) @@ -10578,40 +10608,6 @@ ;; Bit set / bit test instructions -(define_expand "extv" - [(set (match_operand:SI 0 "register_operand") - (sign_extract:SI (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "const8_operand") - (match_operand:SI 3 "const8_operand")))] - "" -{ - /* Handle extractions from %ah et al. */ - if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8) - FAIL; - - /* From mips.md: extract_bit_field doesn't verify that our source - matches the predicate, so check it again here. */ - if (! ext_register_operand (operands[1], VOIDmode)) - FAIL; -}) - -(define_expand "extzv" - [(set (match_operand:SI 0 "register_operand") - (zero_extract:SI (match_operand 1 "ext_register_operand") - (match_operand:SI 2 "const8_operand") - (match_operand:SI 3 "const8_operand")))] - "" -{ - /* Handle extractions from %ah et al. */ - if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8) - FAIL; - - /* From mips.md: extract_bit_field doesn't verify that our source - matches the predicate, so check it again here. */ - if (! ext_register_operand (operands[1], VOIDmode)) - FAIL; -}) - (define_expand "insv" [(set (zero_extract (match_operand 0 "register_operand") (match_operand 1 "const_int_operand") @@ -10656,7 +10652,7 @@ (define_insn "*btsq" [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand")) + (match_operand 1 "const_0_to_63_operand" "J")) (const_int 1)) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_BT || reload_completed)" @@ -10668,7 +10664,7 @@ (define_insn "*btrq" [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand")) + (match_operand 1 "const_0_to_63_operand" "J")) (const_int 0)) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_BT || reload_completed)" @@ -10680,7 +10676,7 @@ (define_insn "*btcq" [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand")) + (match_operand 1 "const_0_to_63_operand" "J")) (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1)))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_BT || reload_completed)" @@ -10696,7 +10692,7 @@ (parallel [(set (zero_extract:DI (match_operand:DI 0 "register_operand") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand")) + (match_operand 1 "const_0_to_63_operand")) (const_int 1)) (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT && !TARGET_USE_BT" @@ -10721,7 +10717,7 @@ (parallel [(set (zero_extract:DI (match_operand:DI 0 "register_operand") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand")) + (match_operand 1 "const_0_to_63_operand")) (const_int 0)) (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT && !TARGET_USE_BT" @@ -10746,7 +10742,7 @@ (parallel [(set (zero_extract:DI (match_operand:DI 0 "register_operand") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand")) + (match_operand 1 "const_0_to_63_operand")) (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1)))) (clobber (reg:CC FLAGS_REG))])] @@ -10767,16 +10763,18 @@ DONE; }) +(define_mode_attr regmode [(SI "k") (DI "q")]) + (define_insn "*bt" [(set (reg:CCC FLAGS_REG) (compare:CCC (zero_extract:SWI48 (match_operand:SWI48 0 "register_operand" "r") (const_int 1) - (match_operand:SWI48 1 "x86_64_nonmemory_operand" "rN")) + (match_operand:SI 1 "nonmemory_operand" "rN")) (const_int 0)))] "TARGET_USE_BT || optimize_function_for_size_p (cfun)" - "bt{}\t{%1, %0|%0, %1}" + "bt{}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "prefix_0f" "1") (set_attr "mode" "")]) @@ -11036,19 +11034,13 @@ FAIL; }) -;; zero_extend in SImode is correct also for DImode, since this is what combine -;; pass generates from shift insn with QImode operand. Actually, the mode -;; of operand 2 (bit offset operand) doesn't matter since bt insn takes -;; appropriate modulo of the bit offset value. - (define_insn_and_split "*jcc_bt" [(set (pc) (if_then_else (match_operator 0 "bt_comparison_operator" [(zero_extract:SWI48 (match_operand:SWI48 1 "register_operand" "r") (const_int 1) - (zero_extend:SI - (match_operand:QI 2 "register_operand" "r"))) + (match_operand:SI 2 "register_operand" "r")) (const_int 0)]) (label_ref (match_operand 3)) (pc))) @@ -11068,20 +11060,18 @@ (label_ref (match_dup 3)) (pc)))] { - operands[2] = simplify_gen_subreg (mode, operands[2], QImode, 0); operands[0] = shallow_copy_rtx (operands[0]); PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0]))); }) -;; Like *jcc_bt, but expect a SImode operand 2 instead of QImode -;; zero extended to SImode. (define_insn_and_split "*jcc_bt_1" [(set (pc) (if_then_else (match_operator 0 "bt_comparison_operator" [(zero_extract:SWI48 (match_operand:SWI48 1 "register_operand" "r") (const_int 1) - (match_operand:SI 2 "register_operand" "r")) + (zero_extend:SI + (match_operand:QI 2 "register_operand" "r"))) (const_int 0)]) (label_ref (match_operand 3)) (pc))) @@ -11101,13 +11091,12 @@ (label_ref (match_dup 3)) (pc)))] { - operands[2] = simplify_gen_subreg (mode, operands[2], SImode, 0); + operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0); operands[0] = shallow_copy_rtx (operands[0]); PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0]))); }) -;; Avoid useless masking of bit offset operand. "and" in SImode is correct -;; also for DImode, this is what combine produces. +;; Avoid useless masking of bit offset operand. (define_insn_and_split "*jcc_bt_mask" [(set (pc) (if_then_else (match_operator 0 "bt_comparison_operator" @@ -11116,7 +11105,7 @@ (const_int 1) (and:SI (match_operand:SI 2 "register_operand" "r") - (match_operand:SI 3 "const_int_operand" "n")))]) + (match_operand 3 "const_int_operand" "n")))]) (label_ref (match_operand 4)) (pc))) (clobber (reg:CC FLAGS_REG))] @@ -11136,76 +11125,6 @@ (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)]) (label_ref (match_dup 4)) (pc)))] -{ - operands[2] = simplify_gen_subreg (mode, operands[2], SImode, 0); - operands[0] = shallow_copy_rtx (operands[0]); - PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0]))); -}) - -(define_insn_and_split "*jcc_btsi_1" - [(set (pc) - (if_then_else (match_operator 0 "bt_comparison_operator" - [(and:SI - (lshiftrt:SI - (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "register_operand" "r")) - (const_int 1)) - (const_int 0)]) - (label_ref (match_operand 3)) - (pc))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_USE_BT || optimize_function_for_size_p (cfun)" - "#" - "&& 1" - [(set (reg:CCC FLAGS_REG) - (compare:CCC - (zero_extract:SI - (match_dup 1) - (const_int 1) - (match_dup 2)) - (const_int 0))) - (set (pc) - (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)]) - (label_ref (match_dup 3)) - (pc)))] -{ - operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0); - operands[0] = shallow_copy_rtx (operands[0]); - PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0]))); -}) - -;; avoid useless masking of bit offset operand -(define_insn_and_split "*jcc_btsi_mask_1" - [(set (pc) - (if_then_else - (match_operator 0 "bt_comparison_operator" - [(and:SI - (lshiftrt:SI - (match_operand:SI 1 "register_operand" "r") - (subreg:QI - (and:SI - (match_operand:SI 2 "register_operand" "r") - (match_operand:SI 3 "const_int_operand" "n")) 0)) - (const_int 1)) - (const_int 0)]) - (label_ref (match_operand 4)) - (pc))) - (clobber (reg:CC FLAGS_REG))] - "(TARGET_USE_BT || optimize_function_for_size_p (cfun)) - && (INTVAL (operands[3]) & 0x1f) == 0x1f" - "#" - "&& 1" - [(set (reg:CCC FLAGS_REG) - (compare:CCC - (zero_extract:SI - (match_dup 1) - (const_int 1) - (match_dup 2)) - (const_int 0))) - (set (pc) - (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)]) - (label_ref (match_dup 4)) - (pc)))] { operands[0] = shallow_copy_rtx (operands[0]); PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0]))); @@ -12748,8 +12667,8 @@ [(set (match_operand:SWI48 0 "register_operand" "=r") (zero_extract:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") - (match_operand:SWI48 2 "const_0_to_255_operand" "n") - (match_operand:SWI48 3 "const_0_to_255_operand" "n"))) + (match_operand 2 "const_0_to_255_operand" "N") + (match_operand 3 "const_0_to_255_operand" "N"))) (clobber (reg:CC FLAGS_REG))] "TARGET_TBM" { -- 2.30.2