From ee4a5c0ea1128a85214db1556b6b1c3622058fad Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 5 May 2022 19:04:22 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 2fe7fa73c..0a714e51d 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -222,4 +222,13 @@ Assuming then that variable-length Vectors are obviously desirable, it becomes a matter of how, not if. Both Cray and NEC SX Aurora went the way of adding explicit Vector opcodes, a style which RVV copied and modernised. In the case of RVV this introduced 192 new -instructions on top of an existing 95+ for base RV64GC. +instructions on top of an existing 95+ for base RV64GC. Adding +200% more instructions than the base ISA seems unwise: at least, +it feels like there should be a better way, particularly on +close inspection of RVV as an example, the basic arithmetic +operations are massively duplicated: scalar-scalar from the base +is joined by both scalar-vector and vector-vector *and* predicate +mask management, and transfer instructions between all the sane, +which goes a long way towards explaining why there are twice as many +Vector instructions in RISC-V as there are in the RV64GC base. + -- 2.30.2