From ee5469c03a547493eca63213248af654d5c1ef2b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 22 Aug 2020 12:09:19 +0100 Subject: [PATCH] r0 zero tests on addis, fails --- src/soc/fu/alu/test/test_pipe_caller.py | 9 +++++++++ src/soc/simulator/test_sim.py | 12 ++++++++++++ 2 files changed, 21 insertions(+) diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index 2c730221..c8d23a35 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -99,6 +99,15 @@ class ALUTestCase(TestAccumulatorBase): initial_regs[2] = random.randint(0, (1 << 64)-1) self.add_case(Program(lst, bigendian), initial_regs) + def case_addis_nonzero_r0(self): + for i in range(10): + imm = random.randint(-(1 << 15), (1 << 15)-1) + lst = [f"addis 3, 0, {imm}"] + print(lst) + initial_regs = [0] * 32 + initial_regs[0] = random.randint(0, (1 << 64)-1) + self.add_case(Program(lst, bigendian), initial_regs) + def case_rand_imm(self): insns = ["addi", "addis", "subfic"] for i in range(10): diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py index b44d059f..ba7b8643 100644 --- a/src/soc/simulator/test_sim.py +++ b/src/soc/simulator/test_sim.py @@ -330,6 +330,18 @@ class GeneralTestCases(FHDLTestCase): with Program(lst, bigendian) as program: self.run_tst_program(program, [12]) + #@unittest.skip("disable") + def test_31_addis(self): + """tests for zero not in register zero + """ + lst = [ "rldicr 0, 0,32,31", + "oris 0, 0,32767", + "ori 0, 0,65535", + "addis 1, 0, 1", + ] + with Program(lst, bigendian) as program: + self.run_tst_program(program, [0, 1]) + def run_tst_program(self, prog, initial_regs=None, initial_sprs=None, initial_mem=None): initial_regs = [0] * 32 -- 2.30.2