From ee7cb7243e6d297051e1f7bc028196b40d470cb3 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 23 Sep 2010 13:00:01 -0700 Subject: [PATCH] [xcc, sim] eliminated zero-extended immediates This is a big commit because it involved rewriting gcc's algorithm for generating constants. --- riscv/decode.h | 5 ++--- riscv/insns/andi.h | 2 +- riscv/insns/ori.h | 2 +- riscv/insns/xori.h | 2 +- 4 files changed, 5 insertions(+), 6 deletions(-) diff --git a/riscv/decode.h b/riscv/decode.h index f99e9eb..125ba76 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -78,7 +78,7 @@ const int JUMP_ALIGN_BITS = 1; // note: bit fields are in little-endian order struct itype_t { - unsigned imm12 : IMM_BITS; + signed imm12 : IMM_BITS; unsigned funct : FUNCT_BITS; unsigned rs1 : GPRID_BITS; unsigned rdi : GPRID_BITS; @@ -139,8 +139,7 @@ union insn_t #define FRDR FR[insn.ftype.rdr] #define FRDI FR[insn.itype.rdi] #define BIGIMM insn.btype.bigimm -#define IMM insn.itype.imm12 -#define SIMM ((int32_t)((uint32_t)insn.itype.imm12<<(32-IMM_BITS))>>(32-IMM_BITS)) +#define SIMM insn.itype.imm12 #define SHAMT (insn.itype.imm12 & 0x3F) #define SHAMTW (insn.itype.imm12 & 0x1F) #define TARGET insn.jtype.target diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h index ada6657..2c90b8b 100644 --- a/riscv/insns/andi.h +++ b/riscv/insns/andi.h @@ -1 +1 @@ -RDI = IMM & RS1; +RDI = SIMM & RS1; diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h index d49c8c1..3ee429d 100644 --- a/riscv/insns/ori.h +++ b/riscv/insns/ori.h @@ -1 +1 @@ -RDI = IMM | RS1; +RDI = SIMM | RS1; diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h index fcf9042..039e1b7 100644 --- a/riscv/insns/xori.h +++ b/riscv/insns/xori.h @@ -1 +1 @@ -RDI = IMM ^ RS1; +RDI = SIMM ^ RS1; -- 2.30.2