From ee815020c438802944fcd29b8b6d8def7e894790 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 20 Apr 2021 12:52:15 +0100 Subject: [PATCH] code-comments for sim.py debug mode --- sim.py | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/sim.py b/sim.py index 3c5a254..2dd1874 100755 --- a/sim.py +++ b/sim.py @@ -176,9 +176,20 @@ class LibreSoCSim(SoCSDRAM): # Debug --------------------------------------------------------------- + # (enable with ./sim.py --debug) if not debug: return + # In debug mode, the DMI interface is used to perform single-step + # and dump of the full register set (MSR, r0-r31, CR, XER, PC). + # by running the exact same program with microwatt and libre-soc + # a straight "diff -u" of the complete progress dumps can be done + # and therefore computation instruction discrepancies found immediately + # and easily, running at "verilator" speed. + # + # the FSM is a bit of a dog's dinner, it relies on the way that DMI + # works, sending requests at periodic intervals. needs work. DoesTheJob. + # setup running of DMI FSM dmi_addr = Signal(4) dmi_din = Signal(64) @@ -361,7 +372,7 @@ class LibreSoCSim(SoCSDRAM): ) ) - if cpu == "libresoc": + if cpu == "libresoc": # XXX TODO: waiting on microwatt upstream patch #self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12600)) self.comb += active_dbg_cr.eq(0) -- 2.30.2