From ee8c4bf5372118f1555b17213d07ad592b820cf8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 15 May 2023 20:38:34 +0100 Subject: [PATCH] RC1 does not exist in CROps, the selection of behaviour *called* RC1 is whether the CROp destination is a 3-bit CR *field* (RC1=0) or if it is a 5-bit CR *bit* (RC1=1) --- src/openpower/decoder/power_insn.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index ab1ead61..9774b6c4 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -2332,8 +2332,8 @@ class CROpMRRM(MRBaseRM, ZZCombinedBaseRM, CROpBaseRM): class CROpFF3RM(FFRc0BaseRM, PredicateBaseRM, VLiBaseRM, DZBaseRM, SZBaseRM, CROpBaseRM): """crop: ffirst 3-bit mode""" - RC1: BaseRM[19] - VLi: BaseRM[20] + VLi: BaseRM[19] + RC1 = 0 inv: BaseRM[21] dz: BaseRM[22] sz: BaseRM[23] @@ -2347,6 +2347,7 @@ class CROpFF3RM(FFRc0BaseRM, PredicateBaseRM, VLiBaseRM, DZBaseRM, SZBaseRM, CRO # Please revisit this code; there is an inactive sketch below. class CROpFF5RM(FFRc1BaseRM, PredicateBaseRM, VLiBaseRM, CROpBaseRM): """cr_op: ffirst 5-bit mode""" + RC1 = 1 # temporary hack VLi: BaseRM[19] inv: BaseRM[21] CR: BaseRM[22, 23] -- 2.30.2