From ee9a60b4eeb1498ebaf5aba4d4f433a99f543ac0 Mon Sep 17 00:00:00 2001 From: Xan Date: Wed, 25 Apr 2018 06:49:00 +0100 Subject: [PATCH] --- A_Harmonised_RVV_and_Packed_SIMD.mdwn | 2 ++ 1 file changed, 2 insertions(+) diff --git a/A_Harmonised_RVV_and_Packed_SIMD.mdwn b/A_Harmonised_RVV_and_Packed_SIMD.mdwn index 02feff5b2..a574d0ebe 100644 --- a/A_Harmonised_RVV_and_Packed_SIMD.mdwn +++ b/A_Harmonised_RVV_and_Packed_SIMD.mdwn @@ -46,6 +46,8 @@ A programmer can configure VCFG with any mix of these alternative configurations The above are pure subsets of valid RVV VCFG configurations (and hence forward compatible between RVP and RVV, whilst also keeping RVP simple). Other useful element types are fixed point fraction types and small integer(4 bit to 7 bit) elements. However these are omitted for now as they aren’t currently part of RVV spec, and the intention of this proposal is to harmonise the Andes SIMD instructions into a subset of RVV. +[[Comparative analysis Harmonised RVP vs Andes Packed SIMD ISA proposal]] + # Comparative analysis with Andes Packed ISA proposal ## 16-bit Arithmetic -- 2.30.2