From eecbc85733e951cf8f909d0be47fbf40d4af8d6f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 10 Jun 2020 15:51:48 +0100 Subject: [PATCH] whitespace --- src/soc/experiment/l0_cache.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index 3b8ff913..d67624bf 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -163,6 +163,7 @@ class DualPortSplitter(Elaboratable): #comb += splitter.sst_valid_i.eq() return m + class DataMergerRecord(Record): """ {data: 128 bit, byte_enable: 16 bit} @@ -173,11 +174,11 @@ class DataMergerRecord(Record): ('en', 16)) Record.__init__(self, Layout(layout), name=name) - self.data.reset_less=True - self.en.reset_less=True + self.data.reset_less = True + self.en.reset_less = True -# TODO: formal verification +# TODO: formal verification class DataMerger(Elaboratable): """DataMerger @@ -617,6 +618,7 @@ class TestL0Cache(unittest.TestCase): run_simulation(dut, l0_cache_ldst(self, dut), vcd_name='test_l0_cache_basic.vcd') + class TestDataMerger(unittest.TestCase): def test_data_merger(self): @@ -642,6 +644,7 @@ class TestDualPortSplitter(unittest.TestCase): #run_simulation(dut, data_merger_merge(dut), # vcd_name='test_dual_port_splitter.vcd') + if __name__ == '__main__': unittest.main(exit=False) -- 2.30.2