From eed24507cc7c77c9be266e5462a8cfec99a89270 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 5 Sep 2022 10:21:20 +0100
Subject: [PATCH] rename "PARALLEL" enums to "PTREDUCE" - parallel tree reduce

---
 src/openpower/consts.py                 | 2 +-
 src/openpower/decoder/power_enums.py    | 2 +-
 src/openpower/decoder/power_svp64_rm.py | 6 +++---
 src/openpower/sv/trans/svp64.py         | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/openpower/consts.py b/src/openpower/consts.py
index 8f0ea054..d1e7f626 100644
--- a/src/openpower/consts.py
+++ b/src/openpower/consts.py
@@ -254,7 +254,7 @@ class SVP64MODEb(_Const):
     BC_CTRTEST = 0 # CTR-test mode
     # reduce mode
     REDUCE = 2  # 0=normal predication 1=reduce mode
-    PARALLEL = 3 # 1=parallel reduce, 0=scalar reduce
+    PTREDUCE = 3 # 1=parallel reduce, 0=scalar reduce
     SVM = 3  # subvector reduce mode 0=independent 1=horizontal
     CRM = 4  # CR mode on reduce (Rc=1) 0=some 1=all
     RG = 4   # Reverse-gear on reduce
diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index bd8dfd18..c02fa6ea 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -297,7 +297,7 @@ class SVP64RMMode(Enum):
     SATURATE = 3
     PREDRES = 4
     BRANCH = 5
-    PARALLEL = 6 # Parallel Reduction
+    PTREDUCE = 6 # Parallel Reduction
 
 
 @unique
diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index 9f804a17..a28d612c 100644
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -180,8 +180,8 @@ class SVP64RMModeDecode(Elaboratable):
                         comb += self.mode.eq(SVP64RMMode.NORMAL)
                         comb += do_pu.eq(mode[SVP64MODE.LDST_PACK]) # Pack mode
                     with m.Elif(mode[SVP64MODE.REDUCE]):
-                        with m.If(mode[SVP64MODE.PARALLEL]):
-                            comb += self.mode.eq(SVP64RMMode.PARALLEL)
+                        with m.If(mode[SVP64MODE.PTREDUCE]):
+                            comb += self.mode.eq(SVP64RMMode.PTREDUCE)
                         with m.Else():
                             comb += self.mode.eq(SVP64RMMode.MAPREDUCE)
                             # Pack only active if SVM=1 & SUBVL>1 & Mode[4]=1
@@ -200,7 +200,7 @@ class SVP64RMModeDecode(Elaboratable):
             with m.If((~is_ldst) &                     # not for LD/ST
                         (mode2 == 0) &                 # first 2 bits == 0
                         mode[SVP64MODE.REDUCE] &       # bit 2 == 1
-                       (~mode[SVP64MODE.PARALLEL])):   # not parallel mapreduce
+                       (~mode[SVP64MODE.PTREDUCE])):   # not parallel mapreduce
                 comb += self.reverse_gear.eq(mode[SVP64MODE.RG]) # finally whew
 
             # extract zeroing
diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index f9a53a7b..15844a26 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1235,7 +1235,7 @@ class SVP64Asm:
             # "mapreduce" modes
             elif sv_mode == 0b00:
                 if parallel:
-                    mode |= (0b1 << SVP64MODE.PARALLEL)  # sets parallel reduce
+                    mode |= (0b1 << SVP64MODE.PTREDUCE)  # sets parallel reduce
                     assert subvl == 0, "TODO sub-vector parallel reduce"
                 else:
                     mode |= (0b1 << SVP64MODE.REDUCE)  # sets mapreduce
-- 
2.30.2