From eedb9456063cb69f1c6a4e40c8694e14e8369e44 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 26 Sep 2018 16:25:04 +0100 Subject: [PATCH] save some cpu cycles by |ing the checks for vectorop together --- riscv/insn_template_sv.cc | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc index 3163a34..6fa9623 100644 --- a/riscv/insn_template_sv.cc +++ b/riscv/insn_template_sv.cc @@ -16,36 +16,37 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc) // REGS_PATTERN is generated by id_regs.py (per opcode) unsigned int floatintmap = REGS_PATTERN; sv_insn_t insn(bits, floatintmap); - bool vectorop = false; reg_t predicate = 0; // identify which regs have had their CSR entries set as vectorised. // really could do with a macro for-loop here... oh well... // integer ops, RD, RS1, RS2, RS3 (use sv_int_tb) + bool vectorop = #ifdef USING_RD - vectorop |= check_reg(true, s_insn.rd()); + check_reg(true, s_insn.rd()) | #endif #ifdef USING_RS1 - vectorop |= check_reg(true, s_insn.rs1()); + check_reg(true, s_insn.rs1()) | #endif #ifdef USING_RS2 - vectorop |= check_reg(true, s_insn.rs2()); + check_reg(true, s_insn.rs2()) | #endif #ifdef USING_RS2 - vectorop |= check_reg(true, s_insn.rs3()); + check_reg(true, s_insn.rs3()) | #endif // fp ops, RD, RS1, RS2, RS3 (use sv_fp_tb) #ifdef USING_FRD - vectorop |= check_reg(false, s_insn.frd()); + check_reg(false, s_insn.frd()) | #endif #ifdef USING_FRS1 - vectorop |= check_reg(false, s_insn.frs1()); + check_reg(false, s_insn.frs1()) | #endif #ifdef USING_FRS2 - vectorop |= check_reg(false, s_insn.rs2()); + check_reg(false, s_insn.rs2()) | #endif #ifdef USING_FRS2 - vectorop |= check_reg(false, s_insn.rs3()); + check_reg(false, s_insn.rs3()) | #endif + false; // save a few cycles by |ing the checks together. // if vectorop is set, one of the regs is not a scalar, // so we must read the VL CSR and do a loop -- 2.30.2