From eee6980a366c669fb22aebd2a5dffaa2af16a103 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 11 Dec 2011 20:17:51 +0100 Subject: [PATCH] fhdl: support Constant parameters for Verilog conversion --- migen/fhdl/verilog.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 8fa9c480..4c22fd4c 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -88,15 +88,17 @@ def _printinstances(ns, i, clk, rst): r += ",\n" firstp = False r += "\t." + p[0] + "(" - if isinstance(p[1], int): + if isinstance(p[1], int) or isinstance(p[1], Constant): r += str(p[1]) - elif isinstance(p[1], basestring): + elif isinstance(p[1], str): r += "\"" + p[1] + "\"" else: raise TypeError r += ")" r += "\n) " - r += ns.GetName(x) + "(\n" + r += ns.GetName(x) + if x.parameters: r += " " + r += "(\n" ports = list(x.ins.items()) + list(x.outs.items()) if x.clkport: ports.append((x.clkport, clk)) -- 2.30.2