From eee6da3dd7d933d98393373e12724cce8236000f Mon Sep 17 00:00:00 2001
From: whitequark <cz@m-labs.hk>
Date: Wed, 26 Dec 2018 12:58:30 +0000
Subject: [PATCH] lib.cdc: add tests for MultiReg.

---
 nmigen/back/pysim.py        |  4 ++++
 nmigen/test/test_lib_cdc.py | 40 +++++++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)
 create mode 100644 nmigen/test/test_lib_cdc.py

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index dd8f24a..27bed92 100644
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -7,6 +7,7 @@ from vcd.gtkw import GTKWSave
 
 from ..tools import flatten
 from ..hdl.ast import *
+from ..hdl.ir import *
 from ..hdl.xfrm import ValueVisitor, StatementVisitor
 
 
@@ -359,6 +360,9 @@ class Simulator:
         self._gtkw_file       = gtkw_file
         self._traces          = traces
 
+        while not isinstance(self._fragment, Fragment):
+            self._fragment = self._fragment.get_fragment(platform=None)
+
     @staticmethod
     def _check_process(process):
         if inspect.isgeneratorfunction(process):
diff --git a/nmigen/test/test_lib_cdc.py b/nmigen/test/test_lib_cdc.py
new file mode 100644
index 0000000..b65c04e
--- /dev/null
+++ b/nmigen/test/test_lib_cdc.py
@@ -0,0 +1,40 @@
+from .tools import *
+from ..hdl.ast import *
+from ..back.pysim import *
+from ..lib.cdc import *
+
+
+class MultiRegTestCase(FHDLTestCase):
+    def test_basic(self):
+        i = Signal()
+        o = Signal()
+        frag = MultiReg(i, o)
+        with Simulator(frag) as sim:
+            sim.add_clock(1e-6)
+            def process():
+                self.assertEqual((yield o), 0)
+                yield i.eq(1)
+                yield Tick()
+                self.assertEqual((yield o), 0)
+                yield Tick()
+                self.assertEqual((yield o), 0)
+                yield Tick()
+                self.assertEqual((yield o), 1)
+            sim.add_process(process)
+
+    def test_basic(self):
+        i = Signal(reset=1)
+        o = Signal()
+        frag = MultiReg(i, o, reset=1)
+        with Simulator(frag) as sim:
+            sim.add_clock(1e-6)
+            def process():
+                self.assertEqual((yield o), 1)
+                yield i.eq(0)
+                yield Tick()
+                self.assertEqual((yield o), 1)
+                yield Tick()
+                self.assertEqual((yield o), 1)
+                yield Tick()
+                self.assertEqual((yield o), 0)
+            sim.add_process(process)
-- 
2.30.2