From eee847759f4e4f8934ba007ad04bb26d614c6f52 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 1 May 2021 21:47:27 +0100 Subject: [PATCH] enable issuer_verilog.py to generate new MMU/DCache config memory type --- src/soc/simple/issuer_verilog.py | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py index 3632d0e6..8c0f8e1f 100644 --- a/src/soc/simple/issuer_verilog.py +++ b/src/soc/simple/issuer_verilog.py @@ -74,8 +74,15 @@ if __name__ == '__main__': if args.mmu: units['mmu'] = 1 # enable MMU - pspec = TestMemPspec(ldst_ifacetype='bare_wb', - imem_ifacetype='bare_wb', + # decide which memory type to configure + if args.mmu: + ldst_ifacetype = 'mmu_cache_wb' + else: + ldst_ifacetype = 'bare_wb' + imem_ifacetype = 'bare_wb' + + pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype, + imem_ifacetype=imem_ifacetype, addr_wid=48, mask_wid=8, # must leave at 64 -- 2.30.2