From eefd89e40fb5d2e23efb5501e38980e526795809 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 10 Nov 2018 06:27:52 +0000 Subject: [PATCH] realised that the bitwidth sign-extension needs to be FROM the source bitwidth not TO the TARGET bitwidth --- riscv/sv_insn_redirect.cc | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index bb8645c..937b232 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -453,12 +453,14 @@ bool sv_proc_t::rv_int_op_prepare(SLHSTYPE const & lhs, SRHSTYPE const & rhs, \ if (bitwidth == xlen) { \ return true; \ } \ + uint8_t lbitwidth = get_bitwidth(lhs.get_elwidth(), xlen); \ + uint8_t rbitwidth = get_bitwidth(lhs.get_elwidth(), xlen); \ if (_insn->signextended) { \ - vlhs = sext_bwid(lhs, bitwidth); \ - vrhs = sext_bwid(rhs, bitwidth); \ + vlhs = sext_bwid(lhs, lbitwidth); \ + vrhs = sext_bwid(rhs, rbitwidth); \ } else { \ - vlhs = zext_bwid(lhs, bitwidth); \ - vrhs = zext_bwid(rhs, bitwidth); \ + vlhs = zext_bwid(lhs, lbitwidth); \ + vrhs = zext_bwid(rhs, rbitwidth); \ } \ return false; \ } \ @@ -556,6 +558,11 @@ OP_MULH_FN(_mulhsu, sv_sreg_t, sv_reg_t, sv_sreg_t, int64_t, uint64_t, int64_t ) OP_MULH_FN(_mulh , sv_sreg_t, sv_sreg_t, sv_sreg_t, int64_t, int64_t, int64_t ) /* 64-bit mulh/mulhu/mulhsu */ +sv_reg_t (sv_proc_t::mulhu)(sv_reg_t const& a, sv_reg_t const& b) +{ + return sv_reg_t(::mulhu(a, b)); +} + sv_sreg_t (sv_proc_t::mulhsu)(sv_sreg_t const& a, sv_reg_t const& b) { return sv_sreg_t(::mulhsu(a, b)); @@ -566,11 +573,6 @@ sv_sreg_t (sv_proc_t::mulh)(sv_sreg_t const& a, sv_sreg_t const& b) return sv_sreg_t(::mulh(a, b)); } -sv_reg_t (sv_proc_t::mulhu)(sv_reg_t const& a, sv_reg_t const& b) -{ - return sv_reg_t(::mulhu(a, b)); -} - sv_reg_t sv_proc_t::rv_sl(sv_reg_t const & lhs, sv_reg_t const & rhs) { return rv_sl(lhs, rhs, xlen); -- 2.30.2