From ef0dcf3bc6380cd6c3454cac7ff881a7454a8281 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 2 Jul 2020 14:36:14 +1000 Subject: [PATCH] Add SYNTH_ECP5_FLAGS option for building This is useful to specify "-noflatten" which helps CI stay under 8GB limit. Normally the AUTONAME stage of yosys will take around 10GB if operating on the whole design. With -noflatten, AUTONAME occurs only per VHDL entity, so only consumes around 3GB of memory. This gets us under the limitations on github actions. More discussion here: https://github.com/antonblanchard/microwatt/pull/209#issuecomment-652186078 Signed-off-by: Michael Neuling --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 769a6bd..20baa24 100644 --- a/Makefile +++ b/Makefile @@ -176,7 +176,7 @@ fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \ synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm) microwatt.json: $(synth_files) $(RAM_INIT_FILE) - $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@" $(uart_files) + $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@ $(SYNTH_ECP5_FLAGS)" $(uart_files) microwatt.v: $(synth_files) $(RAM_INIT_FILE) $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@" $(uart_files) -- 2.30.2