From ef3c4d6c226a0f06ee75963b1d174a786761da71 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 8 Sep 2022 17:09:59 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 2de241756..5ee47abc2 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -154,6 +154,26 @@ Candidates include: * EXT005 (100% free) * brownfield space in EXT019 (25% but NOT recommended) +SVP64, SVP64-Single and SVP64-Reserved will require on their own each 25% of one Major +Opcode for a total of 75% of one Major Opcode. The remaining **Scalar** opcodes, +due to there being two separate sets of operations with 16-bit immediates, will require +the other space totalling two 75% Majors. + +Note critically that: + +* SVP64 may **not** hold any Scalar operations. There is no free available space. + The entire 24-bits is **required** for the abstracted Hardware-Looping Concept + **even when these 24-bits are zero* +* Any Scalar 64-bit instruction (regardless of how it is encoded) is unsafe to + then Vectorise because this creates the situation of Prefixed-Prefixed, + resulting in deep complexity in Hardware Decode at a critical juncture, as + well as bring 96-bit instructions. + +*Three 75% allocations are thus genuinely needed*, all other options are unsuitable +for consideration. + +**Minor Opcodes to fit candidates above** + In order of size, for bitmanip and A/V DSP purposes: * QTY 3of 2-bit XO: ternlogi, crternlogi, grevlogi @@ -161,6 +181,8 @@ In order of size, for bitmanip and A/V DSP purposes: * QTY 8of 5/6-bit (A-Form): xpermi, bincrflut, bmask, fmvis, fishmv, bmrev, Galois Field * QTY 30of 10-bit (X-Form): cldiv/mul, av-min/max/diff, absdac, xperm +Note: Some of the Galois Field operations will require QTY 1of Polynomial SPR. + **EXT004** For biginteger math, two instructions in the same space as "madd*" are to be proposed. -- 2.30.2