From ef50a035f0a9ca829f5a687f3094c0eb2ab442ee Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 30 Oct 2020 10:52:44 +0000 Subject: [PATCH 1/1] add 180nm tapeout to progress --- 3d_gpu.mdwn | 2 ++ 1 file changed, 2 insertions(+) diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn index 3a7d58962..113493e34 100644 --- a/3d_gpu.mdwn +++ b/3d_gpu.mdwn @@ -45,6 +45,8 @@ See [[3d_gpu/articles]] online. # Progress: +* Oct 2020 [[80nm_Oct2020/ls180/]] pinouts decided, code-freeze initiated + for 180nm test ASIC, GDSII deadline set of Dec 2nd. * Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz. DDR3 RAM initialisation successful. 180nm ASIC pinouts started [[180nm_Oct2020/ls180]] * Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation * Jul 2020: first ppc64le "hello world" binary executed. 80,000 gate coriolis2 auto-layout completed with 99.98% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered. -- 2.30.2