From ef5da26089975a6f26096151da9fa94f55fc338f Mon Sep 17 00:00:00 2001 From: Chad Versace Date: Thu, 6 Feb 2020 17:47:59 -0800 Subject: [PATCH] turnip: Add magic register values to tu_physical_device The value of some magic regsiters differ across chipsets. fd6_context manages the differences by initializing them at runtime. Let's do the same. Add to tu_physical_device a subset of those found in fd6_context: RB_UNKNOWN_8E04_blit RB_CCU_CNTL_gmem PC_UNKNOWN_9805 SP_UNKNOWN_A0F8 Part-of: --- src/freedreno/vulkan/tu_blit.c | 3 ++- src/freedreno/vulkan/tu_cmd_buffer.c | 15 ++++++++++----- src/freedreno/vulkan/tu_device.c | 4 ++++ src/freedreno/vulkan/tu_private.h | 7 +++++++ 4 files changed, 23 insertions(+), 6 deletions(-) diff --git a/src/freedreno/vulkan/tu_blit.c b/src/freedreno/vulkan/tu_blit.c index 36d071cbd65..da5fe3b3654 100644 --- a/src/freedreno/vulkan/tu_blit.c +++ b/src/freedreno/vulkan/tu_blit.c @@ -81,6 +81,7 @@ blit_image_info(const struct tu_blit_surf *img, bool src, bool stencil_read) static void emit_blit_step(struct tu_cmd_buffer *cmdbuf, const struct tu_blit *blt) { + struct tu_physical_device *phys_dev = cmdbuf->device->physical_device; struct tu_cs *cs = &cmdbuf->cs; tu_cs_reserve_space(cmdbuf->device, cs, 66); @@ -201,7 +202,7 @@ emit_blit_step(struct tu_cmd_buffer *cmdbuf, const struct tu_blit *blt) A6XX_SP_2D_SRC_FORMAT_MASK(0xf)); tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_8E04, 1); - tu_cs_emit(cs, 0x01000000); + tu_cs_emit(cs, phys_dev->magic.RB_UNKNOWN_8E04_blit); tu_cs_emit_pkt7(cs, CP_BLIT, 1); tu_cs_emit(cs, CP_BLIT_0_OP(BLIT_OP_SCALE)); diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c index 3a0527c1849..6c251757c94 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.c +++ b/src/freedreno/vulkan/tu_cmd_buffer.c @@ -901,6 +901,8 @@ tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index) static void tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs) { + struct tu_physical_device *phys_dev = cmd->device->physical_device; + VkResult result = tu_cs_reserve_space(cmd->device, cs, 256); if (result != VK_SUCCESS) { cmd->record_result = result; @@ -911,7 +913,7 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff); - tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004); + tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, phys_dev->magic.RB_CCU_CNTL_gmem); tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000); tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8); tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0); @@ -1202,6 +1204,7 @@ emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs) static void tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs) { + struct tu_physical_device *phys_dev = cmd->device->physical_device; const struct tu_tiling_config *tiling = &cmd->state.tiling_config; uint32_t x1 = tiling->tile0.offset.x; @@ -1230,10 +1233,10 @@ tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs) update_vsc_pipe(cmd, cs); tu_cs_emit_regs(cs, - A6XX_PC_UNKNOWN_9805(.unknown = 0x1)); + A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805)); tu_cs_emit_regs(cs, - A6XX_SP_UNKNOWN_A0F8(.unknown = 0x1)); + A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8)); tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1); tu_cs_emit(cs, UNK_2C); @@ -1283,6 +1286,8 @@ tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs) static void tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs) { + struct tu_physical_device *phys_dev = cmd->device->physical_device; + VkResult result = tu_cs_reserve_space(cmd->device, cs, 1024); if (result != VK_SUCCESS) { cmd->record_result = result; @@ -1315,9 +1320,9 @@ tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_cs_emit_regs(cs, A6XX_VFD_MODE_CNTL(0)); - tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = 0x1)); + tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805)); - tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = 0x1)); + tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8)); tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1); tu_cs_emit(cs, 0x1); diff --git a/src/freedreno/vulkan/tu_device.c b/src/freedreno/vulkan/tu_device.c index b68f0f4540f..f7e3e10fa4b 100644 --- a/src/freedreno/vulkan/tu_device.c +++ b/src/freedreno/vulkan/tu_device.c @@ -260,6 +260,10 @@ tu_physical_device_init(struct tu_physical_device *device, case 640: device->tile_align_w = 64; device->tile_align_h = 16; + device->magic.RB_UNKNOWN_8E04_blit = 0x01000000; + device->magic.RB_CCU_CNTL_gmem = 0x7c400004; + device->magic.PC_UNKNOWN_9805 = 0x1; + device->magic.SP_UNKNOWN_A0F8 = 0x1; break; default: result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED, diff --git a/src/freedreno/vulkan/tu_private.h b/src/freedreno/vulkan/tu_private.h index 934c907b98c..823f5819b95 100644 --- a/src/freedreno/vulkan/tu_private.h +++ b/src/freedreno/vulkan/tu_private.h @@ -316,6 +316,13 @@ struct tu_physical_device uint32_t tile_align_w; uint32_t tile_align_h; + struct { + uint32_t RB_UNKNOWN_8E04_blit; /* for CP_BLIT's */ + uint32_t RB_CCU_CNTL_gmem; /* for GMEM */ + uint32_t PC_UNKNOWN_9805; + uint32_t SP_UNKNOWN_A0F8; + } magic; + /* This is the drivers on-disk cache used as a fallback as opposed to * the pipeline cache defined by apps. */ -- 2.30.2